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Message-ID: <83fc1482-1867-f66a-78ec-b47ba856f815@codeaurora.org> Date: Mon, 2 Apr 2018 10:57:23 +0530 From: Sricharan R <sricharan@...eaurora.org> To: Bjorn Andersson <bjorn.andersson@...aro.org> Cc: mark.rutland@....com, robh@...nel.org, devicetree@...r.kernel.org, marc.zyngier@....com, catalin.marinas@....com, richardcochran@...il.com, will.deacon@....com, linux@...linux.org.uk, linux-kernel@...r.kernel.org, david.brown@...aro.org, absahu@...eaurora.org, robh+dt@...nel.org, linux-arm-msm@...r.kernel.org, andy.gross@...aro.org, linux-soc@...r.kernel.org, sboyd@...eaurora.org, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH v5 03/13] ARM: dts: ipq4019: Add a few peripheral nodes Hi Bjorn, Thanks a lot for all the reviews. On 3/27/2018 10:20 PM, Bjorn Andersson wrote: > On Fri 23 Mar 03:18 PDT 2018, Sricharan R wrote: >> @@ -172,6 +180,22 @@ >> clock-names = "core", "iface"; >> #address-cells = <1>; >> #size-cells = <0>; >> + dmas = <&blsp_dma 5>, <&blsp_dma 4>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; >> + >> + spi_1: spi@...6000 { /* BLSP1 QUP2 */ >> + compatible = "qcom,spi-qup-v2.2.1"; >> + reg = <0x78b6000 0x600>; >> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, >> + <&gcc GCC_BLSP1_AHB_CLK>; >> + clock-names = "core", "iface"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + dmas = <&blsp_dma 7>, <&blsp_dma 6>; >> + dma-names = "rx", "tx"; >> status = "disabled"; >> }; >> >> @@ -184,9 +208,24 @@ >> clock-names = "iface", "core"; >> #address-cells = <1>; >> #size-cells = <0>; >> + dmas = <&blsp_dma 9>, <&blsp_dma 8>; >> + dma-names = "rx", "tx"; >> status = "disabled"; >> }; >> >> + i2c_1: i2c@...8000 { /* BLSP1 QUP4 */ > > The label, comment and the core clock disagrees on which qup this is. > > Label your nodes based on the SoC naming, not your board - as this will > prevent a future board from using e.g. blsp1 qup2 as i2c (as you already > used the label for that). Sure. will fix. Infact this is QUP3. > >> + compatible = "qcom,i2c-qup-v2.2.1"; >> + reg = <0x78b8000 0x600>; >> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_BLSP1_AHB_CLK>, >> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; > > QUP4? QUP3 > >> + clock-names = "iface", "core"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + dmas = <&blsp_dma 11>, <&blsp_dma 10>; >> + dma-names = "rx", "tx"; >> + status = "disabled"; >> + }; > > Apart from this the patch looks good. Thanks. Regards, Sricharan -- "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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