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Message-ID: <152788239546.225090.5366434047539311619@swboyd.mtv.corp.google.com>
Date:   Fri, 01 Jun 2018 12:46:35 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Chris Packham <chris.packham@...iedtelesis.co.nz>,
        linux-clk@...r.kernel.org
Cc:     Chris Packham <chris.packham@...iedtelesis.co.nz>,
        Michael Turquette <mturquette@...libre.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: mvebu: use correct bit for 98DX3236 NAND

Quoting Chris Packham (2018-05-23 22:23:41)
> The correct fieldbit value for the NAND PLL reload trigger is 27.
> 
> Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
> ---

Applied to clk-next

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