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Message-Id: <1528974029-29617-6-git-send-email-michel.pollet@bp.renesas.com>
Date: Thu, 14 Jun 2018 12:00:21 +0100
From: Michel Pollet <michel.pollet@...renesas.com>
To: linux-renesas-soc@...r.kernel.org,
Simon Horman <horms@...ge.net.au>
Cc: phil.edworthy@...esas.com,
Michel Pollet <buserror+upstream@...il.com>,
Michel Pollet <michel.pollet@...renesas.com>,
Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v1 5/5] ARM: dts: Renesas RZN1D-DB Board: Add UART0 pinmux node
This adds the necessary nodes to add pin configuration for the UART0
of that board.
Signed-off-by: Michel Pollet <michel.pollet@...renesas.com>
---
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
index 4e57ae2..039ec2e 100644
--- a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -8,6 +8,8 @@
/dts-v1/;
+#include <dt-bindings/pinctrl/r9a06g032-pinctrl.h>
+
#include "r9a06g032.dtsi"
/ {
@@ -23,6 +25,17 @@
};
};
+&pinctrl {
+ pinsuart0: pinsuart0 {
+ renesas,rzn1-pinmux-ids = <
+ RZN1_MUX(103, UART0_I) /* UART0_TXD */
+ RZN1_MUX(104, UART0_I) /* UART0_RXD */
+ >;
+ };
+};
+
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinsuart0>;
};
--
2.7.4
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