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Date:   Tue, 21 Aug 2018 09:57:36 -0600
From:   "Jan Beulich" <JBeulich@...e.com>
To:     "Juergen Gross" <jgross@...e.com>
Cc:     "the arch/x86 maintainers" <x86@...nel.org>, <tglx@...utronix.de>,
        "xen-devel" <xen-devel@...ts.xenproject.org>,
        "Boris Ostrovsky" <boris.ostrovsky@...cle.com>, <mingo@...hat.com>,
        <linux-kernel@...r.kernel.org>, <hpa@...or.com>
Subject: Re: [Xen-devel] [PATCH v2 2/2] x86/pae: use 64 bit atomic xchg
 function in native_ptep_get_and_clear

>>> On 21.08.18 at 17:37, <jgross@...e.com> wrote:
> Using only 32-bit writes for the pte will result in an intermediate
> L1TF vulnerable PTE. When running as a Xen PV guest this will at once
> switch the guest to shadow mode resulting in a loss of performance.
> 
> Use arch_atomic64_xchg() instead which will perform the requested
> operation atomically with all 64 bits.
> 
> Some performance considerations according to:
> 
> https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scal 
> able-Processor-throughput-latency.pdf
> 
> The main number should be the latency, as there is no tight loop around
> native_ptep_get_and_clear().
> 
> "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a
> memory operand) isn't mentioned in that document. "lock xadd" (with xadd
> having 3 cycles less latency than xchg) has a latency of 11, so we can
> assume a latency of 14 for "lock xchg".
> 
> Signed-off-by: Juergen Gross <jgross@...e.com>

Reviewed-by: Jan Beulich <jbeulich@...e.com>
with one further remark:

> @@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
>  {
>  	pte_t res;
>  
> -	/* xchg acts as a barrier before the setting of the high bits */
> -	res.pte_low = xchg(&ptep->pte_low, 0);
> -	res.pte_high = ptep->pte_high;
> -	ptep->pte_high = 0;
> +	res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0);

Is the cast on the return value really needed here?

Jan


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