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Message-ID: <153979032539.5275.12064078400966025600@swboyd.mtv.corp.google.com>
Date: Wed, 17 Oct 2018 08:32:05 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: ilia.lin@...il.com
Cc: Rajendra Nayak <rnayak@...eaurora.org>,
Ilia Lin <ilialin@...eaurora.org>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Will Deacon <will.deacon@....com>,
Amit Kucheria <amit.kucheria@...aro.org>,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-soc@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v13 6/8] clk: qcom: cpu-8996: Add support to switch to alternate
PLL
Quoting ilia.lin@...il.com (2018-06-14 14:53:53)
> @@ -227,6 +232,26 @@ clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> return 0;
> }
>
> +int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
static? And name it something like clk_cpu_8996_notifier?
> + void *data)
> +{
> + int ret;
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
> +
> + switch (event) {
> + case PRE_RATE_CHANGE:
> + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
> + break;
> + case POST_RATE_CHANGE:
> + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX);
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
> + return notifier_from_errno(ret);
> +};
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