linux-kernel - Re: [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll

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Message-ID: <154482494548.19322.11090762587126084086@swboyd.mtv.corp.google.com>
Date:   Fri, 14 Dec 2018 14:02:25 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Nicolas Boichat <drinkcat@...omium.org>,
        Rob Herring <robh@...nel.org>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Weiyi Lu <weiyi.lu@...iatek.com>
Cc:     James Liao <jamesjj.liao@...iatek.com>,
        Fan Chen <fan.chen@...iatek.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, linux-clk@...r.kernel.org,
        srv_heupstream@...iatek.com, stable@...r.kernel.org,
        Weiyi Lu <weiyi.lu@...iatek.com>,
        Owen Chen <owen.chen@...iatek.com>
Subject: Re: [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data

Quoting Weiyi Lu (2018-12-09 23:32:31)
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index f0ff5f535c7e..81400601f107 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -69,11 +71,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
>  {
>         int pcwbits = pll->data->pcwbits;
>         int pcwfbits;
> +       int ibits;
>         u64 vco;
>         u8 c = 0;
>  
>         /* The fractional part of the PLL divider. */
> -       pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
> +       ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> +       pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;

This is practically unreadable. It should be changed to an if statement.

>  
>         vco = (u64)fin * pcw;
>  
> @@ -167,9 +171,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
>  static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
>                 u32 freq, u32 fin)
>  {
> -       unsigned long fmin = 1000 * MHZ;
> +       unsigned long fmin = pll->data->fmin ? pll->data->fmin : (1000 * MHZ);
>         const struct mtk_pll_div_table *div_table = pll->data->div_table;
>         u64 _pcw;
> +       int ibits;
>         u32 val;
>  
>         if (freq > pll->data->fmax)
> @@ -193,7 +198,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
>         }
>  
>         /* _pcw = freq * postdiv / fin * 2^pcwfbits */
> -       _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS);
> +       ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS;
> +       _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits);

Similar comment. Readability is low here.