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Message-ID: <20181214020417.2871-2-weiyi.lu@mediatek.com>
Date: Fri, 14 Dec 2018 10:04:15 +0800
From: Weiyi Lu <weiyi.lu@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...eaurora.org>,
Rob Herring <robh@...nel.org>
CC: James Liao <jamesjj.liao@...iatek.com>,
Fan Chen <fan.chen@...iatek.com>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<srv_heupstream@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [resend PATCH v1 0/2] update Mediatek MT2712 clock
This series is based on v4.20-rc1.
Basically, this series is for the 3rd ECO design change of MT2712.
Weiyi Lu (2):
dt-bindings: clock: add clock for MT2712
clk: mediatek: update clock driver of MT2712
drivers/clk/mediatek/clk-mt2712.c | 8 ++++++--
include/dt-bindings/clock/mt2712-clk.h | 3 ++-
2 files changed, 8 insertions(+), 3 deletions(-)
--
2.18.0
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