linux-kernel - RE: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller

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Date:   Tue, 18 Dec 2018 05:33:53 +0000
From:   Naga Sureshkumar Relli <nagasure@...inx.com>
To:     Miquel Raynal <miquel.raynal@...tlin.com>
CC:     Boris Brezillon <boris.brezillon@...tlin.com>,
        "robh@...nel.org" <robh@...nel.org>,
        "richard@....at" <richard@....at>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "marek.vasut@...il.com" <marek.vasut@...il.com>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "nagasuresh12@...il.com" <nagasuresh12@...il.com>,
        Michal Simek <michals@...inx.com>,
        "computersforpeace@...il.com" <computersforpeace@...il.com>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>
Subject: RE: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for
 Arasan NAND Flash Controller

Hi Miquel,

> -----Original Message-----
> From: Miquel Raynal [mailto:miquel.raynal@...tlin.com]
> Sent: Monday, December 17, 2018 10:11 PM
> To: Naga Sureshkumar Relli <nagasure@...inx.com>
> Cc: Boris Brezillon <boris.brezillon@...tlin.com>; robh@...nel.org; richard@....at; linux-
> kernel@...r.kernel.org; marek.vasut@...il.com; linux-mtd@...ts.infradead.org;
> nagasuresh12@...il.com; Michal Simek <michals@...inx.com>;
> computersforpeace@...il.com; dwmw2@...radead.org
> Subject: Re: [LINUX PATCH v12 3/3] mtd: rawnand: arasan: Add support for Arasan
> NAND Flash Controller
> 
> Hi Naga,
> 
> [...]
> 
> > Inserted biterror @ 48/7
> > Successfully corrected 25 bit errors per subpage Inserted biterror @
> > 50/7 ECC failure, invalid data despite read success
> > root@...inx-zc1751-dc2-2018_1:~#
> >
> > But even in this case also, driver is saying ECC failure but read success.
> > That means controller is able to detect errors on read page up to 24 bit only.
> > After that there is no way to say to the upper layers that the page is bad because of the
> limitation in the controller.
> 
> This is more than a "limitation", the design is broken. I am not sure how to support such
> controller, and I am not sure if we even want to.

The number of errors that are correctable is limited by a parameter 't'(total number of errors),
If there is a condition that the number of errors greater than 't', then the controller won't be able to detect that.
I guess this concept is same for other controllers as well.
In Arasan it is limited to 24-bit.

Even, in case of Hamming, it is 1-bit error correction and 2-bit error detection.
What will happen if there are multiple errors(greater than 2-bit)?

Thanks,
Naga Sureshkumar Relli
> 
> > Could you please suggest any alternative to report the errors in that case?
> 
> Shall we support the controller without the hw ECC engine? Boris, any thoughts?
> 
> 
> Thanks,
> Miquèl