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Message-Id: <20190130084203.25053-6-wens@csie.org>
Date: Wed, 30 Jan 2019 16:41:58 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Maxime Ripard <maxime.ripard@...tlin.com>
Cc: linux-sunxi@...glegroups.com, Icenowy Zheng <icenowy@...c.io>,
Andre Przywara <andre.przywara@....com>,
Emmanuel Vadot <manu@...ebsd.org>,
Jagan Teki <jagan@...rulasolutions.com>,
Sergey Matyukevich <geomatsi@...il.com>,
Hauke Mehrtens <hauke@...ke-m.de>,
Chen-Yu Tsai <wens@...e.org>,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 05/10] arm64: dts: allwinner: h5: orange-pi-zero-plus: Add CPU regulator supply
The OrangePi Zero Plus uses a fixed regulator to supply the CPU cores.
The feedback resistor network can be changed by toggling a GPIO line.
This is effectively a GPIO controlled regulator that can change between
roughly 1.1V and 1.3V. The actual voltage is slightly higher. The values
used in the device tree description are based on calculations using the
resistor values from the schematics.
Cc: Hauke Mehrtens <hauke@...ke-m.de>
Signed-off-by: Chen-Yu Tsai <wens@...e.org>
---
This patch is based on the schematics and has not been tested on an
actual board.
---
.../sun50i-h5-orangepi-zero-plus.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
index 1238de25a969..3493eea7cf29 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
@@ -57,6 +57,26 @@
enable-active-high;
gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
};
+
+ reg_vdd_cpux: vdd-cpux {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1108475>;
+ regulator-max-microvolt = <1307810>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
+ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL6 */
+ gpios-states = <0x1>;
+ states = <1108475 0x0
+ 1307810 0x1>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <®_vdd_cpux>;
};
&ehci0 {
--
2.20.1
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