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Date:   Mon, 4 Mar 2019 16:42:10 +0300
From:   Dmitry Osipenko <digetx@...il.com>
To:     Peter De Schrijver <pdeschrijver@...dia.com>
Cc:     Prashant Gaikwad <pgaikwad@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH RE-SEND] clk: tegra: Don't enable already enabled PLLs

04.03.2019 11:18, Peter De Schrijver пишет:
> On Wed, Feb 27, 2019 at 06:15:04PM +0300, Dmitry Osipenko wrote:
>> 24.02.2019 18:32, Dmitry Osipenko пишет:
>>> Initially Common Clock Framework isn't aware of the clock-enable status,
>>> this results in enabling of clocks that were enabled by bootloader. This
>>> is not a big deal for a regular clock-gates, but for PLL's it may have
>>> some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
>>> clock) may result in extra long period of PLL re-locking.
>>>
>>> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
>>> ---
>>
>> Peter (and everyone else), yours r-b and ACK will be appreciated since you kinda already took a look at this patch in the past and were okay with it (IIRC, we had some brief discussion on the #tegra IRC a few months ago), thanks. 
>>
> 
> Acked-By: Peter De Schrijver <pdeschrijver@...dia.com>
> 

Awesome, thanks again!

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