linux-kernel - Re: [PATCH V5 07/16] dt-bindings: PCI: designware: Add binding for CDM register check

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <f340cb14-a6df-340b-ce37-227685f78b80@nvidia.com>
Date:   Tue, 14 May 2019 10:59:31 +0530
From:   Vidya Sagar <vidyas@...dia.com>
To:     Rob Herring <robh@...nel.org>
CC:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Mark Rutland <mark.rutland@....com>,
        Thierry Reding <thierry.reding@...il.com>,
        Jon Hunter <jonathanh@...dia.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Jingoo Han <jingoohan1@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Mikko Perttunen <mperttunen@...dia.com>,
        <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-tegra@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>, <kthota@...dia.com>,
        Manikanta Maddireddy <mmaddireddy@...dia.com>,
        <sagar.tv@...il.com>
Subject: Re: [PATCH V5 07/16] dt-bindings: PCI: designware: Add binding for
 CDM register check

On 5/13/2019 8:45 PM, Rob Herring wrote:
> On Tue, May 7, 2019 at 3:25 AM Vidya Sagar <vidyas@...dia.com> wrote:
>>
>> On 4/26/2019 8:02 PM, Rob Herring wrote:
>>> On Wed, Apr 24, 2019 at 10:49:55AM +0530, Vidya Sagar wrote:
>>>> Add support to enable CDM (Configuration Dependent Module) registers check
>>>> for any data corruption. CDM registers include standard PCIe configuration
>>>> space registers, Port Logic registers and iATU and DMA registers.
>>>> Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
>>>> Version 4.90a
>>>>
>>>> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
>>>> ---
>>>> Changes since [v4]:
>>>> * None
>>>>
>>>> Changes since [v3]:
>>>> * None
>>>>
>>>> Changes since [v2]:
>>>> * Changed flag name from 'cdm-check' to 'enable-cdm-check'
>>>> * Added info about Port Logic and DMA registers being part of CDM
>>>>
>>>> Changes since [v1]:
>>>> * This is a new patch in v2 series
>>>>
>>>>    Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 +++++
>>>>    1 file changed, 5 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>>> index 5561a1c060d0..85b872c42a9f 100644
>>>> --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>>> +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
>>>> @@ -34,6 +34,11 @@ Optional properties:
>>>>    - clock-names: Must include the following entries:
>>>>       - "pcie"
>>>>       - "pcie_bus"
>>>> +- enable-cdm-check: This is a boolean property and if present enables
>>>
>>> This needs a vendor prefix.
>> Why only for this? Since this whole file is for Synopsys DesignWare core based PCIe IP,
>> I thought there is specific prefix required. Am I wrong? Also, CDM checking is a feature
>> of IP and DWC based implementations can choose either to enable this feature at hardware level
>> or not. And whoever enabled it at hardware level (like Tegra194) can set this flag to
>> enable corresponding software support.
> 
> TBC, I meant a Synopsys vendor prefix, not NVIDIA.
> 
> Any property that's not from a common binding should have a vendor
> prefix. That hasn't always happened, so we do have lots of examples
> without.
Ok. got it. I'm going to take care of this in V7 series.

> 
> Rob
>