linux-kernel - Re: [PATCH] arm64: dts: imx8mm: Init rates and parents configs for clocks

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Date:   Tue, 2 Jul 2019 13:26:48 +0000
From:   Abel Vesa <abel.vesa@....com>
To:     Daniel Baluta <daniel.baluta@...il.com>
CC:     Rob Herring <robh@...nel.org>, Mark Rutland <mark.rutland@....com>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Fabio Estevam <fabio.estevam@....com>,
        Anson Huang <anson.huang@....com>,
        dl-linux-imx <linux-imx@....com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Devicetree List <devicetree@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Daniel Baluta <daniel.baluta@....com>
Subject: Re: [PATCH] arm64: dts: imx8mm: Init rates and parents configs for
 clocks

On 19-06-26 15:45:15, Daniel Baluta wrote:
> On Tue, Jun 25, 2019 at 4:42 PM Abel Vesa <abel.vesa@....com> wrote:
> >
> > Add the initial configuration for clocks that need default parent and rate
> > setting. This is based on the vendor tree clock provider parents and rates
> > configuration except this is doing the setup in dts rather than using clock
> > consumer API in a clock provider driver.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@....com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 36 +++++++++++++++++++++++++++++++
> >  1 file changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 232a741..ab92108 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -451,6 +451,42 @@
> >                                          <&clk_ext3>, <&clk_ext4>;
> >                                 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
> >                                               "clk_ext3", "clk_ext4";
> > +                               assigned-clocks = <&clk IMX8MM_CLK_AUDIO_AHB>,
> > +                                               <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
> > +                                               <&clk IMX8MM_SYS_PLL3>,
> > +                                               <&clk IMX8MM_VIDEO_PLL1>,
> > +                                               <&clk IMX8MM_CLK_NOC>,
> > +                                               <&clk IMX8MM_CLK_PCIE1_CTRL>,
> > +                                               <&clk IMX8MM_CLK_PCIE1_PHY>,
> > +                                               <&clk IMX8MM_CLK_CSI1_CORE>,
> > +                                               <&clk IMX8MM_CLK_CSI1_PHY_REF>,
> > +                                               <&clk IMX8MM_CLK_CSI1_ESC>,
> > +                                               <&clk IMX8MM_CLK_DISP_AXI>,
> > +                                               <&clk IMX8MM_CLK_DISP_APB>;
> > +                               assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
> > +                                               <0>,
> Isn't there a macro for 0? (dummy clock?)

I don't know about any such macro. If you're referring to IMX8MM_CLK_DUMMY,
that can't be used here since all I want here is to skip setting a parent to
the  IMX8MM_CLK_IPG_AUDIO_ROOT. If I use IMX8MM_CLK_DUMMY (along with &clk)
it will set the parent to IMX8MM_CLK_DUMMY and that's not what's needed here.

This is in accordance to the documentation:

Documentation/devicetree/bindings/clock/clock-bindings.txt:

"To skip setting parent or rate of a clock its corresponding entry should be
set to 0, or can be omitted if it is not followed by any non-zero entry."

> 
> 
> > +                                               <0>,
> > +                                               <0>,
> > +                                               <&clk IMX8MM_SYS_PLL3_OUT>,
> > +                                               <&clk IMX8MM_SYS_PLL2_250M>,
> > +                                               <&clk IMX8MM_SYS_PLL2_100M>,
> > +                                               <&clk IMX8MM_SYS_PLL2_1000M>,
> > +                                               <&clk IMX8MM_SYS_PLL2_1000M>,
> > +                                               <&clk IMX8MM_SYS_PLL1_800M>,
> > +                                               <&clk IMX8MM_SYS_PLL2_1000M>,
> > +                                               <&clk IMX8MM_SYS_PLL1_800M>;
> > +                               assigned-clock-rates = <400000000>,
> > +                                                       <400000000>,
> > +                                                       <750000000>,
> > +                                                       <594000000>,
> > +                                                       <0>,
> > +                                                       <0>,
> > +                                                       <0>,
> > +                                                       <0>,
> > +                                                       <0>,
> > +                                                       <0>,
> > +                                                       <500000000>,
> > +                                                       <200000000>;
> >                         };
> >
> >                         src: reset-controller@...90000 {
> > --
> > 2.7.4
> >