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Message-ID: <20190917153650.GF3524@sirena.co.uk>
Date:   Tue, 17 Sep 2019 16:36:50 +0100
From:   Mark Brown <broonie@...nel.org>
To:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>
Cc:     robh+dt@...nel.org, mark.rutland@....com,
        linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
        qi-ming.wu@...el.com
Subject: Re: [PATCH v1 2/2] spi: cadence-qspi: Add QSPI support for Intel LGM
 SoC

On Tue, Sep 17, 2019 at 10:11:28AM +0800, Ramuthevar, Vadivel MuruganX wrote:

> *    spi-cadence.c* in *drivers/spi/*, which supports very old legacy
> cadence-spi based devices(normal)
> *    cadence-quadspi.c(drivers/mtd/spi-nor/)* : specific support to SPI-NOR
> flash with new spi-nor layer.
>     all the API's in this driver purely on spi-nor specific, so couldn't 
> proceed to adapt.

Are these completely separate IPs or are they just different versions of
the same IP?

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