[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <eeefa79b-0a3b-5d62-3a1b-c1e9dcb03aa7@linux.intel.com>
Date: Wed, 18 Sep 2019 13:59:06 +0800
From: "Ramuthevar, Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@...ux.intel.com>
To: Mark Brown <broonie@...nel.org>
Cc: robh+dt@...nel.org, mark.rutland@....com,
linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, cheol.yong.kim@...el.com,
qi-ming.wu@...el.com
Subject: Re: [PATCH v1 2/2] spi: cadence-qspi: Add QSPI support for Intel LGM
SoC
Hi Mark,
Thank you for the review comments.
On 17/9/2019 11:36 PM, Mark Brown wrote:
> On Tue, Sep 17, 2019 at 10:11:28AM +0800, Ramuthevar, Vadivel MuruganX wrote:
>
>> * spi-cadence.c* in *drivers/spi/*, which supports very old legacy
>> cadence-spi based devices(normal)
>> * cadence-quadspi.c(drivers/mtd/spi-nor/)* : specific support to SPI-NOR
>> flash with new spi-nor layer.
>> all the API's in this driver purely on spi-nor specific, so couldn't
>> proceed to adapt.
> Are these completely separate IPs or are they just different versions of
> the same IP?
These are same IPs , but different features Enabled/Disabled depends
upon the SoC vendors.
for e.g: Intel LGM SoC uses the same IP, but without DMA and Direct
access controller.
also dedicated support to flash devices.
Best regards
Vadivel
Powered by blists - more mailing lists