linux-kernel - RE: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2 cache way enabled

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Message-ID: <CH2PR13MB3368B844DB765AE9166C1F1A8C2E0@CH2PR13MB3368.namprd13.prod.outlook.com>
Date:   Mon, 23 Dec 2019 08:53:20 +0000
From:   Yash Shah <yash.shah@...ive.com>
To:     Palmer Dabbelt <palmerdabbelt@...gle.com>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "Paul Walmsley ( Sifive)" <paul.walmsley@...ive.com>,
        "aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
        "bmeng.cn@...il.com" <bmeng.cn@...il.com>,
        "allison@...utok.net" <allison@...utok.net>,
        "alexios.zavras@...el.com" <alexios.zavras@...el.com>,
        Atish Patra <Atish.Patra@....com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        Greg KH <gregkh@...uxfoundation.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2
 cache way enabled

> -----Original Message-----
> From: Palmer Dabbelt <palmerdabbelt@...gle.com>
> Sent: 14 December 2019 07:43
> To: Yash Shah <yash.shah@...ive.com>
> Cc: robh+dt@...nel.org; mark.rutland@....com; Paul Walmsley ( Sifive)
> <paul.walmsley@...ive.com>; aou@...s.berkeley.edu;
> bmeng.cn@...il.com; allison@...utok.net; alexios.zavras@...el.com; Atish
> Patra <Atish.Patra@....com>; tglx@...utronix.de; Greg KH
> <gregkh@...uxfoundation.org>; devicetree@...r.kernel.org; linux-
> riscv@...ts.infradead.org; linux-kernel@...r.kernel.org; Yash Shah
> <yash.shah@...ive.com>
> Subject: Re: [PATCH 2/2] riscv: cacheinfo: Add support to determine no. of L2
> cache way enabled
> 
> On Mon, 09 Dec 2019 03:25:06 PST (-0800), yash.shah@...ive.com wrote:
> > In order to determine the number of L2 cache ways enabled at runtime,
> > implement a private attribute using cache_get_priv_group() in
> > cacheinfo framework. Reading this attribute
> ("number_of_ways_enabled")
> > will return the number of enabled L2 cache ways at runtime.
> >
> > Signed-off-by: Yash Shah <yash.shah@...ive.com>
> > ---
> >  arch/riscv/include/asm/sifive_l2_cache.h |  2 ++
> >  arch/riscv/kernel/cacheinfo.c            | 31
> +++++++++++++++++++++++++++++++
> >  drivers/soc/sifive/sifive_l2_cache.c     |  5 +++++
> >  3 files changed, 38 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/sifive_l2_cache.h
> > b/arch/riscv/include/asm/sifive_l2_cache.h
> > index 04f6748..217a42f 100644
> > --- a/arch/riscv/include/asm/sifive_l2_cache.h
> > +++ b/arch/riscv/include/asm/sifive_l2_cache.h
> > @@ -10,6 +10,8 @@
> >  extern int register_sifive_l2_error_notifier(struct notifier_block
> > *nb);  extern int unregister_sifive_l2_error_notifier(struct
> > notifier_block *nb);
> >
> > +int sifive_l2_largest_wayenabled(void);
> 
> I thought the plan was to get this stuff out of arch/riscv?  It looks like it only
> got half-way done.

Are you suggesting to move this header file out of "/arch/riscv/include/asm/" to maybe "include/soc/sifive/"?

- Yash