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Date:   Fri, 14 Feb 2020 18:39:23 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     agross@...nel.org, bjorn.andersson@...aro.org,
        devicetree@...r.kernel.org, jshriram@...eaurora.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org, mark.rutland@....com,
        mturquette@...libre.com, psodagud@...eaurora.org,
        robh+dt@...nel.org, tdas@...eaurora.org, tsoni@...eaurora.org,
        vnkgutta@...eaurora.org
Subject: Re: [PATCH v2 6/7] clk: qcom: gcc: Add global clock controller
 driver for SM8250

On 05-02-20, 11:40, Stephen Boyd wrote:

> > +static const struct clk_parent_data gcc_parent_data_2[] = {
> > +       { .fw_name = "bi_tcxo" },
> > +       { .fw_name = "sleep_clk", .name = "sleep_clk" },
> 
> Please drop .name

Yup, will do

> > +static const struct clk_parent_data gcc_parent_data_5[] = {
> > +       { .fw_name = "bi_tcxo" },
> > +       { .hw = &gpll0.clkr.hw },
> > +       { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
> 
> Why have .name? Pleas remove it.

Dropped...

> > +       { .hw = &gpll0_out_even.clkr.hw },
> > +       { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
> 
> Please drop these test inputs. I don't see any reason why they're listed.

Dropped this and rest.

> > +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
> > +       .halt_reg = 0x48198,
> > +       .halt_check = BRANCH_HALT_VOTED,
> > +       .clkr = {
> > +               .enable_reg = 0x52000,
> > +               .enable_mask = BIT(0),
> > +               .hw.init = &(struct clk_init_data){
> > +                       .name = "gcc_sys_noc_cpuss_ahb_clk",
> > +                       .parent_data = &(const struct clk_parent_data){
> > +                               .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
> > +                       },
> > +                       .num_parents = 1,
> > +                       .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
> > +                       .ops = &clk_branch2_ops,
> > +               },
> > +       },
> > +};
> 
> Is there a need for this clk to be exposed? Why can't we just turn the
> bit on in probe and ignore it after that? I'd prefer to not have
> CLK_IS_CRITICAL in this driver unless necessary.

yeah moved it as setting a bit in probe..

> > +       /*
> > +        * Keep the clocks always-ON
> > +        * GCC_VIDEO_AHB_CLK, GCC_CAMERA_AHB_CLK, GCC_DISP_AHB_CLK,
> > +        * GCC_CPUSS_DVM_BUS_CLK, GCC_GPU_CFG_AHB_CLK
> > +        */
> > +       regmap_update_bits(regmap, 0x0b004, BIT(0), BIT(0));
> > +       regmap_update_bits(regmap, 0x0b008, BIT(0), BIT(0));
> > +       regmap_update_bits(regmap, 0x0b00c, BIT(0), BIT(0));
> > +       regmap_update_bits(regmap, 0x4818c, BIT(0), BIT(0));
> > +       regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
> 
> These look like the AHB clks above that we just enabled and then ignore.

right, I think these are rest of the always-on clocks

-- 
~Vinod

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