linux-kernel - Re: [PATCH 2/3] x86/split_lock: Bits in IA32_CORE

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Date:   Fri, 17 Apr 2020 00:06:47 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Tony Luck <tony.luck@...el.com>
Cc:     Tony Luck <tony.luck@...el.com>, Ingo Molnar <mingo@...nel.org>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Borislav Petkov <bp@...en8.de>, H Peter Anvin <hpa@...or.com>,
        Ashok Raj <ashok.raj@...el.com>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        Sean Christopherson <sean.j.christopherson@...el.com>,
        Andy Lutomirski <luto@...nel.org>,
        linux-kernel@...r.kernel.org, x86@...nel.org
Subject: Re: [PATCH 2/3] x86/split_lock: Bits in IA32_CORE_CAPABILITIES are not architectural

Tony Luck <tony.luck@...el.com> writes:
> The Intel Software Developers' Manual erroneously listed bit 5 of the
> IA32_CORE_CAPABILITIES register as an architectural feature. It is
> not.

TBH. I'm really pissed off by that. We ask Intel for the past 20 years
that this non-enumerability and model checking has to stop.

Especially for the split lock festure we got assured that the Icelakes
are the only models which need the cpu match because it was too late to
add the capability bit.

> Features enumerated by IA32_CORE_CAPABILITIES are model specific and
> implementation details may vary in different cpu models. Thus it is only
> safe to trust features after checking the CPU model.

What's the point of the IA32_CORE_CAPABILITIES check if we need a model
match to figure out whether IA32_CORE_CAPABILITIES bit 5 is valid to
enumerate split lock detection?

IOW, are we going to see CPUs which end up in the match list and have
bit 5 cleared in IA32_CORE_CAPABILITIES?

Thanks,

        tglx