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Date:   Thu, 7 May 2020 01:36:36 +0300
From:   Serge Semin <fancer.lancer@...il.com>
To:     Randy Dunlap <rdunlap@...radead.org>
Cc:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
        Paul Burton <paulburton@...nel.org>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Arnd Bergmann <arnd@...db.de>,
        Rob Herring <robh+dt@...nel.org>, linux-mips@...r.kernel.org,
        devicetree@...r.kernel.org, Lee Jones <lee.jones@...aro.org>,
        Michael Walle <michael@...le.cc>,
        Lubomir Rintel <lkundrak@...sk>,
        Matti Vaittinen <matti.vaittinen@...rohmeurope.com>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Tony Xie <tony.xie@...k-chips.com>, Wen He <wen.he_1@....com>,
        Mike Looijmans <mike.looijmans@...ic.nl>,
        Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
        Joel Stanley <joel@....id.au>, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 3/4] clk: Add Baikal-T1 CCU PLLs driver

Hello,

On Wed, May 06, 2020 at 03:27:57PM -0700, Randy Dunlap wrote:
> Hi,
> 
> Typo(s):
> 
> On 5/6/20 3:22 PM, Serge Semin wrote:
> > diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig
> > new file mode 100644
> > index 000000000000..e1257af9f49e
> > --- /dev/null
> > +++ b/drivers/clk/baikal-t1/Kconfig
> > @@ -0,0 +1,30 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +config CLK_BAIKAL_T1
> > +	bool "Baikal-T1 Clocks Control Unit interface"
> > +	depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
> > +	default MIPS_BAIKAL_T1
> > +	help
> > +	  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
> > +	  responsible for the chip subsystems clocking and resetting. It
> > +	  consists of multiple global clock domains, which can be reset by
> > +	  means of the CCU control registers. These domains and devices placed
> > +	  in them are fed with clocks generated by a hierarchy of PLLs,
> > +	  configurable and fixed clock dividers. Enable this option to be able
> > +	  to select Baikal-T1 CCU PLLs and Dividers drivers.
> > +
> > +if CLK_BAIKAL_T1
> > +
> > +config CLK_BT1_CCU_PLL
> > +	bool "Baikal-T1 CCU PLLs support"
> > +	select MFD_SYSCON
> > +	default MIPS_BAIKAL_T1
> > +	help
> > +	  Enable this to support the PLLs embedded into the Baikal-T1 SoC
> > +	  System Controller. These are five PLLs placed at the root of the
> > +	  clocks hierarchy, right after an external reference osciallator
> 
> 	                                                      oscillator

Fixed. Thanks.

> 
> > +	  (normally of 25MHz). They are used to generate high frequency
> > +	  signals, which are either directly wired to the consumers (like
> > +	  CPUs, DDR, etc) or passed over the clock dividers to be only then
> 
> and while you are here:
> 
>                      etc.)

Thanks again.

-Sergey

> 
> > +	  used as an individual reference clock of a target device.
> > +
> > +endif
> 
> thanks.
> -- 
> ~Randy
> 

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