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Date: Sat, 4 Jul 2020 09:39:50 +0300 From: Pekka Enberg <penberg@...il.com> To: guoren@...nel.org Cc: palmerdabbelt@...gle.com, Paul Walmsley <paul.walmsley@...ive.com>, Anup Patel <anup@...infault.org>, greentime.hu@...ive.com, zong.li@...ive.com, me@...ki.ch, bjorn.topel@...il.com, atish.patra@....com, linux-riscv@...ts.infradead.org, Guo Ren <guoren@...ux.alibaba.com>, LKML <linux-kernel@...r.kernel.org>, linux-csky@...r.kernel.org Subject: Re: [PATCH V1 0/5] riscv: Add k/uprobe supported On Sat, Jul 4, 2020 at 6:34 AM <guoren@...nel.org> wrote: > The patchset includes kprobe/uprobe support and some related fixups. Nice! On Sat, Jul 4, 2020 at 6:34 AM <guoren@...nel.org> wrote: > There is no single step exception in riscv ISA, so utilize ebreak to > simulate. Some pc related instructions couldn't be executed out of line > and some system/fence instructions couldn't be a trace site at all. > So we give out a reject list and simulate list in decode-insn.c. Can you elaborate on what you mean by this? Why would you need a single-step facility for kprobes? Is it for executing the instruction that was replaced with a probe breakpoint? Also, the "Debug Specification" [1] specifies a single-step facility for RISC-V -- why is that not useful for implementing kprobes? 1. https://riscv.org/specifications/debug-specification/ - Pekka
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