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Date:   Sat, 4 Jul 2020 09:39:50 +0300
From:   Pekka Enberg <>
Cc:, Paul Walmsley <>,
        Anup Patel <>,,,,,,,
        Guo Ren <>,
        LKML <>,
Subject: Re: [PATCH V1 0/5] riscv: Add k/uprobe supported

On Sat, Jul 4, 2020 at 6:34 AM <> wrote:
> The patchset includes kprobe/uprobe support and some related fixups.


On Sat, Jul 4, 2020 at 6:34 AM <> wrote:
> There is no single step exception in riscv ISA, so utilize ebreak to
> simulate. Some pc related instructions couldn't be executed out of line
> and some system/fence instructions couldn't be a trace site at all.
> So we give out a reject list and simulate list in decode-insn.c.

Can you elaborate on what you mean by this? Why would you need a
single-step facility for kprobes? Is it for executing the instruction
that was replaced with a probe breakpoint?

Also, the "Debug Specification" [1] specifies a single-step facility
for RISC-V -- why is that not useful for implementing kprobes?


- Pekka

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