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Date: Tue, 25 Aug 2020 08:47:57 +0800 From: Cathy Zhang <cathy.zhang@...el.com> To: kvm@...r.kernel.org, linux-kernel@...r.kernel.org, x86@...nel.org Cc: pbonzini@...hat.com, sean.j.christopherson@...el.com, gregkh@...uxfoundation.org, tglx@...utronix.de, tony.luck@...el.com, dave.hansen@...el.com, kyung.min.park@...el.com, ricardo.neri-calderon@...ux.intel.com, vkuznets@...hat.com, wanpengli@...cent.com, jmattson@...gle.com, joro@...tes.org, mingo@...hat.com, bp@...en8.de, hpa@...or.com, jpoimboe@...hat.com, ak@...ux.intel.com, ravi.v.shankar@...el.com, Cathy Zhang <cathy.zhang@...el.com> Subject: [PATCH v4 1/2] x86/cpufeatures: Enumerate TSX suspend load address tracking instructions From: Kyung Min Park <kyung.min.park@...el.com> Intel TSX suspend load tracking instructions aim to give a way to choose which memory accesses do not need to be tracked in the TSX read set. Add TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration. A processor supports Intel TSX suspend load address tracking if CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK are available when this feature is present. The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo. This instruction is currently documented in the the latest "extensions" manual (ISE). It will appear in the "main" manual (SDM) in the future. Signed-off-by: Kyung Min Park <kyung.min.park@...el.com> Signed-off-by: Cathy Zhang <cathy.zhang@...el.com> Reviewed-by: Tony Luck <tony.luck@...el.com> --- Changes since v3: * N/A Changes since v2: * Shorten documentation names for readability. Links to documentation can be found in the cover letter. (Dave Hansen) --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2901d5d..83fc9d3 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -368,6 +368,7 @@ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ +#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ -- 1.8.3.1
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