linux-kernel - Re: [PATCH v2 0/8] clk: at91: adapt for dvfs

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Message-ID: <6f8d8f2c-997c-7942-c894-319e8b96188f@microchip.com>
Date:   Thu, 5 Nov 2020 14:48:02 +0000
From:   <Claudiu.Beznea@...rochip.com>
To:     <mturquette@...libre.com>, <sboyd@...nel.org>,
        <Nicolas.Ferre@...rochip.com>, <alexandre.belloni@...tlin.com>,
        <Ludovic.Desroches@...rochip.com>, <robh+dt@...nel.org>
CC:     <linux-clk@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <Eugen.Hristev@...rochip.com>
Subject: Re: [PATCH v2 0/8] clk: at91: adapt for dvfs

Hi,

Please ignore this series for the moment as I will have to run few more
tests on it. Sorry for the noise!

Thank you,
Claudiu Beznea

On 04.11.2020 19:45, Claudiu Beznea wrote:
> Hi,
> 
> SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
> obtained from CPU PLL. The hardware block diagram for clock feeding the
> CPU is as follows:
> 
>                                +--------+
>                            +-->|divider1|--> CPU clock
>                            |   +--------+
> +--------+   +----------+  |   +--------+
> |CPU PLL |-->|prescaller|--+-->|divider0|--> MCK0 clock
> +--------+   +----------+      +--------+
> 
> When switching CPU clock frequencies the MCK0 is also changed by DVFS
> driver to avoid its over/under clocking (depending on CPU clock frequency
> requested by DVFS algorithms). Some of IPs feed by MCK0 are MCK0 glich
> aware, some are not. For this MCK0 was removed from the parents list of
> the IPs which are not MCK0 glitch aware (patch 5/8).
> 
> This series adapt AT91 clocks (mostly sam9x60-pll and master clock drivers)
> so that runtime changes of these clocks to be allowed.
> 
> The CPU clock was registered from prescaller clock (see above diagram)
> and no software control has been added for divider1 because the frequencies
> supported by SAMA7G5's CPU could be directly obtained from CPU PLL +
> prescaller.
> 
> On top of this series I also added a fix for sama7g5.c code (patch 1/8).
> Please let me know if you would like me to send this one separtely (it
> would be nice if this fix could be integrated in 5.10).
> 
> Thank you,
> Claudiu Beznea
> 
> Changes in v2:
> - s/at91rm9200_mck_lock/at91sam9260_mck_lock in patch 7/8
> 
> Claudiu Beznea (6):
>   clk: at91: sama7g5: fix compilation error
>   clk: at91: clk-sam9x60-pll: allow runtime changes for pll
>   clk: at91: sama7g5: remove mck0 from parent list of other clocks
>   clk: at91: sama7g5: decrease lower limit for MCK0 rate
>   clk: at91: clk-master: re-factor master clock
>   clk: at91: sama7g5: register cpu clock
> 
> Eugen Hristev (2):
>   dt-bindings: clock: at91: add sama7g5 pll defines
>   clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and
>     referenced in DT
> 
>  drivers/clk/at91/at91rm9200.c      |  20 ++-
>  drivers/clk/at91/at91sam9260.c     |  24 ++-
>  drivers/clk/at91/at91sam9g45.c     |  30 ++--
>  drivers/clk/at91/at91sam9n12.c     |  34 ++--
>  drivers/clk/at91/at91sam9rl.c      |  22 ++-
>  drivers/clk/at91/at91sam9x5.c      |  27 +++-
>  drivers/clk/at91/clk-master.c      | 323 +++++++++++++++++++++++++++++++------
>  drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++--
>  drivers/clk/at91/dt-compat.c       |  15 +-
>  drivers/clk/at91/pmc.h             |  20 ++-
>  drivers/clk/at91/sam9x60.c         |  35 ++--
>  drivers/clk/at91/sama5d2.c         |  41 +++--
>  drivers/clk/at91/sama5d3.c         |  37 +++--
>  drivers/clk/at91/sama5d4.c         |  39 +++--
>  drivers/clk/at91/sama7g5.c         | 139 +++++++++-------
>  include/dt-bindings/clock/at91.h   |  11 ++
>  16 files changed, 692 insertions(+), 227 deletions(-)
>