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Message-ID: <fe37e295-9d74-160c-9b16-bbd5dcd5a638@microchip.com>
Date: Thu, 3 Dec 2020 14:40:07 +0000
From: <Tudor.Ambarus@...rochip.com>
To: <michael@...le.cc>, <linux-mtd@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>,
<boris.brezillon@...labora.com>, <stable@...r.kernel.org>
Subject: Re: [PATCH v7 1/7] mtd: spi-nor: sst: fix BPn bits for the
SST25VF064C
On 12/3/20 1:00 AM, Michael Walle wrote:
> --- a/drivers/mtd/spi-nor/sst.c
> +++ b/drivers/mtd/spi-nor/sst.c
> @@ -18,7 +18,8 @@ static const struct flash_info sst_parts[] = {
> SECT_4K | SST_WRITE) },
> { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64,
> SECT_4K | SST_WRITE) },
> - { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
> + { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128,
> + SECT_4K | SPI_NOR_4BIT_BP) },
And I would put 1/7 after 4/7, so that I can set the locking flags
in some order: SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP. We first indicate
that the flash supports locking, and then what kind of locking, BP3,
and not the other way around.
anyway, just cosmetics
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