linux-kernel - RE: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection

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Message-ID: <dfc2fc320c96408e86c2f23b21979a5b@intel.com>
Date:   Sat, 16 Jan 2021 08:19:35 +0000
From:   "Zhang, Rui" <rui.zhang@...el.com>
To:     Peter Zijlstra <peterz@...radead.org>
CC:     "mingo@...hat.com" <mingo@...hat.com>,
        "acme@...nel.org" <acme@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "alexander.shishkin@...ux.intel.com" 
        <alexander.shishkin@...ux.intel.com>,
        "jolsa@...hat.com" <jolsa@...hat.com>,
        "namhyung@...nel.org" <namhyung@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "kan.liang@...ux.intel.com" <kan.liang@...ux.intel.com>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: RE: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection



> -----Original Message-----
> From: Peter Zijlstra <peterz@...radead.org>
> Sent: Saturday, January 16, 2021 4:03 AM
> To: Zhang, Rui <rui.zhang@...el.com>
> Cc: mingo@...hat.com; acme@...nel.org; mark.rutland@....com;
> alexander.shishkin@...ux.intel.com; jolsa@...hat.com;
> namhyung@...nel.org; linux-kernel@...r.kernel.org; x86@...nel.org;
> kan.liang@...ux.intel.com; ak@...ux.intel.com
> Subject: Re: [PATCH 2/3] perf/x86/rapl: Fix energy counter detection
> Importance: High
> 
> On Fri, Jan 15, 2021 at 05:22:07PM +0800, Zhang Rui wrote:
> > In the RAPL ENERGY_COUNTER MSR, only the lower 32bits represent the
> > energy counter, and the higher 32bits are reserved.
> >
> > Add the MSR mask for these MSRs to fix a problem that the RAPL PMU
> > events are added erroneously when higher 32bits contain non-zero value.
> 
> Why would these high bits be non-zero?

On SPR platform, the high bits of Psys energy counter are reused for other purpose.
High bits for other RAPL domains energy counters still return 0.

I didn't mention this because I thought this patch should be okay as a generic fix.

Thanks,
rui