[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <161729942370.11933.4405261208235446764.b4-ty@canonical.com>
Date: Thu, 1 Apr 2021 19:50:52 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Rob Herring <robh+dt@...nel.org>,
Dmitry Osipenko <digetx@...il.com>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-tegra@...r.kernel.org
Subject: Re: [PATCH v2 0/6] NVIDIA Tegra memory improvements
On Wed, 31 Mar 2021 02:04:39 +0300, Dmitry Osipenko wrote:
> This series replaces the raw voltage regulator with a power domain that
> will be managing SoC core voltage. The core power domain patches are still
> under review, but it's clear at this point that this is the way we will
> implement the DVFS support.
>
> The remaining Tegra20 memory bindings are converted to schema. I also
> made a small improvement to the memory drivers.
>
> [...]
Applied, thanks!
[1/6] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain
commit: d46cf7106c4979117e108336dfadcaf57d23f9ed
[2/6] dt-bindings: memory: tegra30: emc: Replace core regulator with power domain
commit: c19137a97e39a9cdf24c9feb580af4564997c1f9
[3/6] dt-bindings: memory: tegra124: emc: Replace core regulator with power domain
commit: 749d01cd0b796adb69d68e9079520f4f95b17cd2
[6/6] memory: tegra: Print out info-level once per driver probe
commit: 06949d1d9accbc7d3a029536650162bbca30151b
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
Powered by blists - more mailing lists