lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <a4126d48-f5fa-d20c-9874-fc8ac78febb0@canonical.com>
Date:   Thu, 3 Jun 2021 21:45:01 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To:     Thierry Reding <thierry.reding@...il.com>
Cc:     Dmitry Osipenko <digetx@...il.com>, linux-tegra@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PULL] memory: tegra: Changes for v5.14-rc1

On 03/06/2021 16:37, Thierry Reding wrote:
> Hi Krzysztof,
> 
> The following changes since commit 6efb943b8616ec53a5e444193dccf1af9ad627b5:
> 
>   Linux 5.13-rc1 (2021-05-09 14:17:44 -0700)
> 
> are available in the Git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-5.14-memory
> 
> for you to fetch changes up to b4f74b59b99fab61ab97fc0e506f349579d8fefc:
> 
>   memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() (2021-06-03 14:24:03 +0200)
> 
> Thanks,
> Thierry
> 
> ----------------------------------------------------------------
> memory: tegra: Changes for v5.14-rc1
> 
> This stable tag contains Dmitry's power domain work, including all the
> necessary dependencies from the regulator, clock and ARM SoC trees.
> 
> ----------------------------------------------------------------
> Dmitry Osipenko (18):
>       clk: tegra30: Use 300MHz for video decoder by default
>       clk: tegra: Fix refcounting of gate clocks
>       clk: tegra: Ensure that PLLU configuration is applied properly
>       clk: tegra: Halve SCLK rate on Tegra20
>       clk: tegra: Don't allow zero clock rate for PLLs
>       clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
>       clk: tegra: Mark external clocks as not having reset control
>       clk: tegra: Don't deassert reset on enabling clocks
>       regulator: core: Add regulator_sync_voltage_rdev()
>       soc/tegra: regulators: Bump voltages on system reboot
>       soc/tegra: Add stub for soc_is_tegra()
>       soc/tegra: Add devm_tegra_core_dev_init_opp_table()
>       soc/tegra: fuse: Add stubs needed for compile-testing
>       clk: tegra: Add stubs needed for compile-testing
>       memory: tegra: Fix compilation warnings on 64bit platforms
>       memory: tegra: Enable compile testing for all drivers
>       memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()
>       memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table()
> 
> Thierry Reding (3):
>       Merge branch 'for-5.14/regulator' into for-5.14/soc
>       Merge branch 'for-5.14/clk' into for-5.14/memory
>       Merge branch 'for-5.14/soc' into for-5.14/memory
> 

Thanks, pulled.

Best regards,
Krzysztof

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ