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Message-ID: <CACRpkdYGD3s_7QEMa2cgx+5XFFJK_VwcN_km-Dbtr35hCSoFtw@mail.gmail.com>
Date:   Wed, 11 Aug 2021 17:12:16 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Piyush Mehta <piyush.mehta@...inx.com>
Cc:     Arnd Bergmann <arnd@...db.de>, Zou Wei <zou_wei@...wei.com>,
        Greg KH <gregkh@...uxfoundation.org>,
        Michal Simek <michal.simek@...inx.com>, wendy.liang@...inx.com,
        Nobuhiro Iwamatsu <iwamatsu@...auri.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Rob Herring <robh+dt@...nel.org>, rajan.vaja@...inx.com,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, git <git@...inx.com>,
        Srinivas Goud <sgoud@...inx.com>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2 3/3] gpio: modepin: Add driver support for modepin GPIO controller

On Thu, Aug 5, 2021 at 7:43 PM Piyush Mehta <piyush.mehta@...inx.com> wrote:

> This patch adds driver support for the zynqmp modepin GPIO controller.
> GPIO modepin driver set and get the value and status of the PS_MODE pin,
> based on device-tree pin configuration. These four mode pins are
> configurable as input/output. The mode pin has a control register, which
> have lower four-bits [0:3] are configurable as input/output, next four-bits
> can be used for reading the data  as input[4:7], and next setting the
> output pin state output[8:11].
>
> Signed-off-by: Piyush Mehta <piyush.mehta@...inx.com>
> ---
> Changes in v2:

After discussion with Michal:
Reviewed-by: Linus Walleij <linus.walleij@...aro.org>

Yours,
Linus Walleij

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