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Message-ID: <CAGXv+5Fj69MQroMZV5ecpEg7cBcin0rA7C6XNCZcvcHebV-HQg@mail.gmail.com>
Date: Mon, 23 Aug 2021 20:20:24 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: Chun-Jie Chen <chun-jie.chen@...iatek.com>
Cc: Matthias Brugger <matthias.bgg@...il.com>,
Stephen Boyd <sboyd@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>,
Rob Herring <robh+dt@...nel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@...ts.infradead.org>,
LKML <linux-kernel@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>, linux-clk@...r.kernel.org,
Devicetree List <devicetree@...r.kernel.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [v2 13/24] clk: mediatek: Add MT8195 ipesys clock support
On Fri, Aug 20, 2021 at 7:25 PM Chun-Jie Chen
<chun-jie.chen@...iatek.com> wrote:
>
> Add MT8195 ipesys clock controller which provides clock gate
> control for ipe IP block.
Could you describe "ipe" in generic terms?
ChenYu
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