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Message-ID: <202110100346.stpC3gQ5-lkp@intel.com>
Date: Sun, 10 Oct 2021 03:04:56 +0800
From: kernel test robot <lkp@...el.com>
To: Dan Williams <dan.j.williams@...el.com>, linux-cxl@...r.kernel.org
Cc: kbuild-all@...ts.01.org, Ben Widawsky <ben.widawsky@...el.com>,
linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org, hch@....de
Subject: Re: [PATCH v3 05/10] cxl/pci: Make more use of cxl_register_map
Hi Dan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on ed97afb53365cd03dde266c9644334a558fe5a16]
url: https://github.com/0day-ci/linux/commits/Dan-Williams/cxl_pci-refactor-for-reusability/20211010-004521
base: ed97afb53365cd03dde266c9644334a558fe5a16
config: parisc-randconfig-r012-20211010 (attached as .config)
compiler: hppa-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/049a2765e60ef3807f8e4b8d04f2b70d90b38c94
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Dan-Williams/cxl_pci-refactor-for-reusability/20211010-004521
git checkout 049a2765e60ef3807f8e4b8d04f2b70d90b38c94
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=parisc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
In file included from include/linux/printk.h:555,
from include/linux/kernel.h:19,
from arch/parisc/include/asm/bug.h:5,
from include/linux/bug.h:5,
from include/linux/io.h:11,
from include/linux/io-64-nonatomic-lo-hi.h:5,
from drivers/cxl/pci.c:3:
drivers/cxl/pci.c: In function 'cxl_pci_map_regblock':
>> drivers/cxl/pci.c:330:22: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 5 has type 'resource_size_t' {aka 'unsigned int'} [-Wformat=]
330 | dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/dynamic_debug.h:134:29: note: in definition of macro '__dynamic_func_call'
134 | func(&id, ##__VA_ARGS__); \
| ^~~~~~~~~~~
include/linux/dynamic_debug.h:166:9: note: in expansion of macro '_dynamic_func_call'
166 | _dynamic_func_call(fmt,__dynamic_dev_dbg, \
| ^~~~~~~~~~~~~~~~~~
include/linux/dev_printk.h:155:9: note: in expansion of macro 'dynamic_dev_dbg'
155 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/dev_printk.h:155:30: note: in expansion of macro 'dev_fmt'
155 | dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
| ^~~~~~~
drivers/cxl/pci.c:330:9: note: in expansion of macro 'dev_dbg'
330 | dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
| ^~~~~~~
drivers/cxl/pci.c:330:70: note: format string is defined here
330 | dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
| ~~~~^
| |
| long long unsigned int
| %#x
vim +330 drivers/cxl/pci.c
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 308
049a2765e60ef3 drivers/cxl/pci.c Ben Widawsky 2021-10-09 309 static void __iomem *cxl_pci_map_regblock(struct pci_dev *pdev,
049a2765e60ef3 drivers/cxl/pci.c Ben Widawsky 2021-10-09 310 struct cxl_register_map *map)
1b0a1a2a193400 drivers/cxl/pci.c Ben Widawsky 2021-04-07 311 {
f8a7e8c29be873 drivers/cxl/pci.c Ira Weiny 2021-05-27 312 void __iomem *addr;
049a2765e60ef3 drivers/cxl/pci.c Ben Widawsky 2021-10-09 313 int bar = map->barno;
049a2765e60ef3 drivers/cxl/pci.c Ben Widawsky 2021-10-09 314 struct device *dev = &pdev->dev;
049a2765e60ef3 drivers/cxl/pci.c Ben Widawsky 2021-10-09 315 resource_size_t offset = map->block_offset;
1b0a1a2a193400 drivers/cxl/pci.c Ben Widawsky 2021-04-07 316
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 317 /* Basic sanity check that BAR is big enough */
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 318 if (pci_resource_len(pdev, bar) < offset) {
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 319 dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar,
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 320 &pdev->resource[bar], (unsigned long long)offset);
a0270407a9b3b5 drivers/cxl/pci.c Dan Williams 2021-10-09 321 return NULL;
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 322 }
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 323
30af97296f48d8 drivers/cxl/pci.c Ira Weiny 2021-06-03 324 addr = pci_iomap(pdev, bar, 0);
f8a7e8c29be873 drivers/cxl/pci.c Ira Weiny 2021-05-27 325 if (!addr) {
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 326 dev_err(dev, "failed to map registers\n");
f8a7e8c29be873 drivers/cxl/pci.c Ira Weiny 2021-05-27 327 return addr;
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 328 }
8adaf747c9f0b4 drivers/cxl/mem.c Ben Widawsky 2021-02-16 329
f8a7e8c29be873 drivers/cxl/pci.c Ira Weiny 2021-05-27 @330 dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n",
f8a7e8c29be873 drivers/cxl/pci.c Ira Weiny 2021-05-27 331 bar, offset);
6630d31c912ed2 drivers/cxl/pci.c Ben Widawsky 2021-05-20 332
30af97296f48d8 drivers/cxl/pci.c Ira Weiny 2021-06-03 333 return addr;
30af97296f48d8 drivers/cxl/pci.c Ira Weiny 2021-06-03 334 }
30af97296f48d8 drivers/cxl/pci.c Ira Weiny 2021-06-03 335
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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