linux-kernel - Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET

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Message-ID: <20211014082224.GA30554@lst.de>
Date:   Thu, 14 Oct 2021 10:22:24 +0200
From:   "hch@....de" <hch@....de>
To:     "Tian, Kevin" <kevin.tian@...el.com>
Cc:     "hch@....de" <hch@....de>, Jason Gunthorpe <jgg@...dia.com>,
        Jean-Philippe Brucker <jean-philippe@...aro.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>,
        "jasowang@...hat.com" <jasowang@...hat.com>,
        "kwankhede@...dia.com" <kwankhede@...dia.com>,
        "Jiang, Dave" <dave.jiang@...el.com>,
        "Raj, Ashok" <ashok.raj@...el.com>,
        "corbet@....net" <corbet@....net>,
        "parav@...lanox.com" <parav@...lanox.com>,
        Alex Williamson <alex.williamson@...hat.com>,
        "lkml@...ux.net" <lkml@...ux.net>,
        "david@...son.dropbear.id.au" <david@...son.dropbear.id.au>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "Tian, Jun J" <jun.j.tian@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "lushenming@...wei.com" <lushenming@...wei.com>,
        "pbonzini@...hat.com" <pbonzini@...hat.com>,
        "robin.murphy@....com" <robin.murphy@....com>
Subject: Re: [RFC 10/20] iommu/iommufd: Add IOMMU_DEVICE_GET_INFO

On Thu, Oct 14, 2021 at 08:13:03AM +0000, Tian, Kevin wrote:
> Based on above information my interpretation is that existing 
> DMA API manages coherency per device and It's not designed for
> devices which are coherent in nature but also set PCI no-snoop
> for selective traffic. Then the new DMA_ATTR_NO_SNOOP, once
> set in dma_map, allows the driver to follow non-coherent
> semantics even when the device itself is considered coherent.
> 
> Does it capture the whole story correct? 

Yes.

> > > What I don't really understand is why ARM, with an IOMMU that supports
> > > PTE WB, has devices where dev_is_dma_coherent() == false ?
> > 
> > Because no IOMMU in the world can help that fact that a periphal on the
> > SOC is not part of the cache coherency protocol.
> 
> but since DMA goes through IOMMU then isn't IOMMU the one who
> should decide the final cache coherency? What would be the case
> if the IOMMU sets WB while the peripheral doesn't want it?

No.  And IOMMU deal with address translation, it can't paper over
a fact that there is no coherency possible.