linux-kernel - Re: [PATCH v2 7/7] memory: renesas-rpc-if: Add support for RZ/G2L

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Date:   Tue, 2 Nov 2021 23:25:40 +0000
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Wolfram Sang <wsa+renesas@...g-engineering.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Rob Herring <robh+dt@...nel.org>,
        Vignesh Raghavendra <vigneshr@...com>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Richard Weinberger <richard@....at>,
        Mark Brown <broonie@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Sergei Shtylyov <sergei.shtylyov@...il.com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
        linux-mtd@...ts.infradead.org,
        linux-spi <linux-spi@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Prabhakar <prabhakar.csengg@...il.com>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH v2 7/7] memory: renesas-rpc-if: Add support for RZ/G2L

Hi Wolfram,

Thank you for the review.

On Tue, Nov 2, 2021 at 11:48 AM Wolfram Sang
<wsa+renesas@...g-engineering.com> wrote:
>
> Hi Prabhakar,
>
> > +#define RPCIF_PHYADD         0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
> > +#define RPCIF_PHYWR          0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
>
> Nice detailed research, thanks! Minor nit: Keep the sorting
> alphabetical: D3, E3, V3M.
>
> > +static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
> > +{
> > +     u32 data;
> > +
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
> > +
> > +     regmap_read(rpc->regmap, RPCIF_PHYCNT, &data);
> > +     regmap_write(rpc->regmap, RPCIF_PHYCNT, data | RPCIF_PHYCNT_CKSEL(3));
> > +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
> > +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
> > +}
>
> Still magic values here. Don't you have them explained in your Gen3
> documentation? It is tables 62.16 and 62.17 in my versions.
>
Oops I missed that, does the below look good?

#define RPCIF_PHYADD_ADD_MD 0x00
#define RPCIF_PHYADD_ADD_RDLSEL 0x22
#define RPCIF_PHYADD_ADD_FDLSEL 0x24
#define RPCIF_PHYADD_ADD_RDLMON 0x26
#define RPCIF_PHYADD_ADD_FDLMON 0x28

#define RPCIF_PHYADD_ACCEN BIT(31)
#define RPCIF_PHYADD_RW BIT(30)
#define RPCIF_PHYADD_ADD(v) (v & 0x3f)

#define RPCIF_MD_PHYREGEN_VAL 0xa539
#define RPCIF_MD_PHYREGEN(v) ((v & 0xffff) << 16)

#define RPCIF_RDLSEL_QSPI0DLTAPSEL(v) (v & 0x1f)
#define RPCIF_RDLSEL_QSPI0DLSETEN(v) ((v & 0x1) << 7)
#define RPCIF_RDLSEL_QSPI1DLTAPSEL(v) ((v & 0x1f) << 8)
#define RPCIF_RDLSEL_QSPI1DLSETEN(v) ((v & 0x1) << 15)

#define RPCIF_FDLSEL_QSPI0DLTAPSEL(v) (v & 0x1f)
#define RPCIF_FDLSEL_QSPI0DLSETEN(v) ((v & 0x1) << 7)
#define RPCIF_FDLSEL_QSPI1DLTAPSEL(v) ((v & 0x1f) << 8)
#define RPCIF_FDLSEL_QSPI1DLSETEN(v) ((v & 0x1) << 15)

> +     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
> +     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
>
For the above do you have any suggestions? As I couldn't find any
details about it or shall I just go with magic numbers for now?

> Other than these, looks good.
>
thanks, once we agree upon above I shall re-spin v3.

Cheers,
Prabhakar

> Thanks,
>
>    Wolfram