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Message-ID: <6d5986ac-68ef-5537-8882-f34b8436d16a@infradead.org>
Date: Wed, 3 Nov 2021 22:09:36 -0700
From: Randy Dunlap <rdunlap@...radead.org>
To: Qin Jian <qinjian@...lus1.com>, robh+dt@...nel.org
Cc: mturquette@...libre.com, sboyd@...nel.org, maz@...nel.org,
p.zabel@...gutronix.de, linux@...linux.org.uk, broonie@...nel.org,
arnd@...db.de, linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, wells.lu@...plus.com
Subject: Re: [PATCH v4 06/10] clk: Add Sunplus SP7021 clock driver
On 11/3/21 7:57 PM, Qin Jian wrote:
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index c5b3dc973..1cd7ae7a3 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -334,6 +334,15 @@ config COMMON_CLK_VC5
> This driver supports the IDT VersaClock 5 and VersaClock 6
> programmable clock generators.
>
> +config COMMON_CLK_SP7021
> + bool "Clock driver for Sunplus SP7021 SoC"
> + help
> + This driver supports the Sunplus SP7021 SoC clocks.
> + It implemented SP7021 PLLs/gate.
implements
> + Not all features of the PLL are currently supported
> + by the driver.
> + This driver is selected automatically by platform config.
--
~Randy
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