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Message-ID: <20220207183046.GA408682@bhelgaas>
Date: Mon, 7 Feb 2022 12:30:46 -0600
From: Bjorn Helgaas <helgaas@...nel.org>
To: Bharat Kumar Gogada <bharat.kumar.gogada@...inx.com>
Cc: linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
lorenzo.pieralisi@....com, bhelgaas@...gle.com, michals@...inx.com
Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root
Port driver
In subject, possibly:
PCI: xilinx-cpm: Add Versal CPM5 Root Port support
since you're adding support for a *device*, not for a *driver*.
On Mon, Feb 07, 2022 at 09:42:50AM +0530, Bharat Kumar Gogada wrote:
> Xilinx Versal Premium series has CPM5 block which supports Root port
> functioning at Gen5 speed.
> Xilinx Versal CPM5 has few changes with existing CPM block.
> - CPM5 has dedicated register space for control and status registers.
> - CPM5 legacy interrupt handling needs additional register bit
> to enable and handle legacy interrupts.
s/Root port/Root Port/ to be consistent.
Add blank line between paragraphs.
Bjorn
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