linux-kernel - RE: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port

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Message-ID: <BY5PR02MB694796AB6735769F20D11E3FA52D9@BY5PR02MB6947.namprd02.prod.outlook.com>
Date:   Tue, 8 Feb 2022 10:38:07 +0000
From:   Bharat Kumar Gogada <bharatku@...inx.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        Michal Simek <michals@...inx.com>
Subject: RE: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal CPM5
 Root Port

> Subject: Re: [PATCH 1/2] PCI: xilinx-cpm: Update YAML schemas for Versal
> CPM5 Root Port
> 
> It looks like the subject line convention here would be something
> like:
> 
>   dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
> 
> (From "git log --oneline Documentation/devicetree/bindings/pci/")
> 
> On Mon, Feb 07, 2022 at 09:42:48AM +0530, Bharat Kumar Gogada wrote:
> > Xilinx Versal Premium series has CPM5 block which supports Root port
> > functioning at Gen5 speed.
> > Add support for YAML schemas documentation for Versal CPM5 Root Port
> driver.
> 
> s/Root port/Root Port/ to be consistent.
> Add blank line between paragraphs.
> 
Thanks Bjorn, will do the changes in next patch.

Regards,
Bharat