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Message-ID: <b2e32685-73a6-98be-50be-5121c67431ed@linaro.org>
Date:   Tue, 19 Apr 2022 12:39:48 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Jacky Huang <ychuang3@...oton.com>, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, ychuang570808@...il.com
Cc:     robh+dt@...nel.org, sboyd@...nel.org, krzk+dt@...nel.org,
        arnd@...db.de, olof@...om.net, will@...nel.org, soc@...nel.org,
        cfli0@...oton.com
Subject: Re: [PATCH v3 2/5] dt-bindings: clock: Document MA35D1 clock
 controller bindings
On 19/04/2022 12:12, Jacky Huang wrote:
>>> +
>>> +  assigned-clock-rates:
>>> +    minItems: 5
>>> +    maxItems: 5
>>> +
>>> +  nuvoton,clk-pll-mode:
>>> +    A list of PLL operation mode corresponding to DDRPLL, APLL, EPLL,
>>> +    and VPLL in sequential.
>> This does not look like a binding which was tested. Read
>> "writing-schema" and test your bindings.
> 
> "nuvoton,clk-pll-mode" is a nonstandard property used to describe the 
> operation mode of
> corresponding PLLs.
> 
> (According to Device tree Specification section "2.2.4 Properties"
> Nonstandard property names should specify a unique string prefix, such 
> as a stock ticker symbol, identifying the name of
> the company or organization that defined the property. Examples:
I am not saying about property name. I replied under some description
below which fails to build.
Instead please test your bindings.
Best regards,
Krzysztof
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