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Message-ID: <de389d34-22c1-5c62-d6c2-bfb256924a97@amd.com>
Date:   Fri, 27 May 2022 07:59:32 +0530
From:   Ravi Bangoria <ravi.bangoria@....com>
To:     Arnaldo Carvalho de Melo <acme@...nel.org>, peterz@...radead.org
Cc:     irogers@...gle.com, rrichter@....com, mingo@...hat.com,
        mark.rutland@....com, jolsa@...nel.org, namhyung@...nel.org,
        tglx@...utronix.de, bp@...en8.de, james.clark@....com,
        leo.yan@...aro.org, kan.liang@...ux.intel.com, ak@...ux.intel.com,
        eranian@...gle.com, like.xu.linux@...il.com, x86@...nel.org,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
        sandipan.das@....com, ananth.narayan@....com, kim.phillips@....com,
        santosh.shukla@....com, Ravi Bangoria <ravi.bangoria@....com>
Subject: Re: [PATCH v4 3/5] perf/x86/ibs: Add new IBS register bits into
 header

Hi Arnaldo,

On 26-May-22 9:19 PM, Arnaldo Carvalho de Melo wrote:
> Em Mon, May 23, 2022 at 09:09:43AM +0530, Ravi Bangoria escreveu:
>> IBS support has been enhanced with two new features in upcoming uarch:
>> 1. DataSrc extension and 2. L3 miss filtering. Additional set of bits
>> has been introduced in IBS registers to exploit these features. Define
>> these new bits into arch/x86/ header.
> 
> You mentioned the kernel bits were already applied and this was a tools
> only series, this one slipped into :-)

Right. V1 had a single patch containing both kernel and tools file changes
and thus Peter might not have applied it. How should we pursues it?

Thanks,
Ravi

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