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Message-Id: <20220705130036.1384656-1-michael@walle.cc>
Date: Tue, 5 Jul 2022 15:00:36 +0200
From: Michael Walle <michael@...le.cc>
To: herve.codina@...tlin.com
Cc: alexandre.belloni@...tlin.com, claudiu.beznea@...rochip.com,
devicetree@...r.kernel.org, gregkh@...uxfoundation.org,
horatiu.vultur@...rochip.com, krzysztof.kozlowski+dt@...aro.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
mturquette@...libre.com, nicolas.ferre@...rochip.com,
robh+dt@...nel.org, sboyd@...nel.org, thomas.petazzoni@...tlin.com,
Michael Walle <michael@...le.cc>
Subject: Re: [PATCH v5 1/3] clk: lan966x: Fix the lan966x clock gate register address
> The register address used for the clock gate register is the base
> register address coming from first reg map (ie. the generic
> clock registers) instead of the second reg map defining the clock
> gate register.
>
> Use the correct clock gate register address.
>
> Fixes: 5ad5915dea00 ("clk: lan966x: Extend lan966x clock driver for clock gating support")
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
Tested-by: Michael Walle <michael@...le.cc>
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