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Date: Wed, 31 Aug 2022 09:27:10 +0200 From: Peter Zijlstra <peterz@...radead.org> To: Like Xu <like.xu.linux@...il.com> Cc: Sean Christopherson <seanjc@...gle.com>, kvm@...r.kernel.org, Kan Liang <kan.liang@...ux.intel.com>, Paolo Bonzini <pbonzini@...hat.com>, Ingo Molnar <mingo@...hat.com>, Arnaldo Carvalho de Melo <acme@...nel.org>, Mark Rutland <mark.rutland@....com>, Alexander Shishkin <alexander.shishkin@...ux.intel.com>, Jiri Olsa <jolsa@...nel.org>, Namhyung Kim <namhyung@...nel.org>, Thomas Gleixner <tglx@...utronix.de>, Borislav Petkov <bp@...en8.de>, Dave Hansen <dave.hansen@...ux.intel.com>, x86@...nel.org, "'H . Peter Anvin'" <hpa@...or.com>, linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH RESEND] perf/x86/core: Completely disable guest PEBS via guest's global_ctrl On Wed, Aug 31, 2022 at 11:35:24AM +0800, Like Xu wrote: > From: Like Xu <likexu@...cent.com> > > When a guest PEBS counter is cross-mapped by a host counter, software > will remove the corresponding bit in the arr[global_ctrl].guest and > expect hardware to perform a change of state "from enable to disable" > via the msr_slot[] switch during the vmx transaction. > > The real world is that if user adjust the counter overflow value small > enough, it still opens a tiny race window for the previously PEBS-enabled > counter to write cross-mapped PEBS records into the guest's PEBS buffer, > when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff) > to switch into the enabled state, while the arr[pebs_enable].guest has not. > > Close this window by clearing invalid bits in the arr[global_ctrl].guest. > > Cc: linux-perf-users@...r.kernel.org > Cc: Kan Liang <kan.liang@...ux.intel.com> > Cc: Peter Zijlstra <peterz@...radead.org> > Cc: Sean Christopherson <seanjc@...gle.com> > Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations") > Signed-off-by: Like Xu <likexu@...cent.com> > --- Thanks!
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