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Date:   Wed, 31 Aug 2022 00:38:51 +0000
From:   Hongxing Zhu <hongxing.zhu@....com>
To:     Philipp Zabel <p.zabel@...gutronix.de>,
        "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "robh@...nel.org" <robh@...nel.org>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "alexander.stein@...tq-group.com" <alexander.stein@...tq-group.com>,
        "marex@...x.de" <marex@...x.de>,
        "richard.leitner@...ux.dev" <richard.leitner@...ux.dev>
CC:     "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support

> -----Original Message-----
> From: Philipp Zabel <p.zabel@...gutronix.de>
> Sent: 2022年8月31日 0:46
> To: Hongxing Zhu <hongxing.zhu@....com>; l.stach@...gutronix.de;
> bhelgaas@...gle.com; lorenzo.pieralisi@....com; robh@...nel.org;
> shawnguo@...nel.org; vkoul@...nel.org; alexander.stein@...tq-group.com;
> marex@...x.de; richard.leitner@...ux.dev
> Cc: linux-phy@...ts.infradead.org; devicetree@...r.kernel.org;
> linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; kernel@...gutronix.de; dl-linux-imx
> <linux-imx@....com>
> Subject: Re: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST
> support
> 
> Hi,
> 
> On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> > On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST
> > bit(BIT3) of SRC_PCIEPHY_RCR is 1b'1.
> > But i.MX8MP has one inversed default value 1b'0 of PERST bit.
> >
> > And the PERST bit should be kept 1b'1 after power and clocks are stable.
> > So fix the i.MX8MP PCIe PHY PERST support here.
> >
> > Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> > Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> > Reviewed-by: Philipp Zabel <p.zabel@...gutronix.de>
> > Tested-by: Marek Vasut <marex@...x.de>
> > Tested-by: Richard Leitner <richard.leitner@...data.com>
> > Tested-by: Alexander Stein <alexander.stein@...tq-group.com>
> 
> I've applied this patch to the reset/fixes branch.
> 

Thanks a lot.

Best Regards
Richard Zhu

> regards
> Philipp

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