linux-kernel - RE: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485 support to quad-uart driver.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <PH0PR11MB509668B72B3B85C2966D36909B369@PH0PR11MB5096.namprd11.prod.outlook.com>
Date:   Tue, 1 Nov 2022 14:53:25 +0000
From:   <Tharunkumar.Pasumarthi@...rochip.com>
To:     <ilpo.jarvinen@...ux.intel.com>,
        <Kumaravel.Thiagarajan@...rochip.com>
CC:     <gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
        <andy.shevchenko@...il.com>, <u.kleine-koenig@...gutronix.de>,
        <johan@...nel.org>, <wander@...hat.com>,
        <etremblay@...tech-controls.com>, <macro@...am.me.uk>,
        <geert+renesas@...der.be>, <jk@...abs.org>,
        <phil.edworthy@...esas.com>, <lukas@...ner.de>,
        <linux-kernel@...r.kernel.org>, <linux-serial@...r.kernel.org>,
        <UNGLinuxDriver@...rochip.com>
Subject: RE: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
 support to quad-uart driver.

> From: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
> Sent: Monday, October 3, 2022 2:34 PM
> To: Kumaravel Thiagarajan - I21417
> <Kumaravel.Thiagarajan@...rochip.com>
> Subject: Re: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
> support to quad-uart driver.
> 
> [Some people who received this message don't often get email from
> ilpo.jarvinen@...ux.intel.com. Learn why this is important at
> https://aka.ms/LearnAboutSenderIdentification ]
> 
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
> 
> > +     if (rs485->flags & SER_RS485_ENABLED) {
> > +             memset(rs485->padding, 0, sizeof(rs485->padding));
> 
> Core handles this for you.

I went through the code and it seems like this is not taken care by the core.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.

> > +             if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) {
> > +                     data |= ADCL_CFG_POL_SEL;
> > +                     rs485->flags |=  SER_RS485_RTS_AFTER_SEND;
> > +             } else {
> > +                     rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
> > +             }
> 
> Core handles that flags sanitization for you.

I went through the code and it seems like this is not taken care by the core.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.

> > +     } else {
> > +             memset(rs485, 0, sizeof(*rs485));
> 
> Core handles this.

I went through the code and it seems like this is not taken care by the core.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.

> > +     writeb(data, (port->membase + ADCL_CFG_REG));
> > +     port->rs485 = *rs485;
> 
> Core handles this.

I went through the code and it seems like this is not taken care by the core.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_config' callback?
This has not been done since we do not need all the configurations done inside 'serial8250_em485_config'.

Thanks,
Tharun Kumar P