linux-kernel - Re: [PATCH v2] ASoC: wm8962: Wait for updated value of WM8962

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Message-ID: <20221109162412.GG10437@ediswmail.ad.cirrus.com>
Date:   Wed, 9 Nov 2022 16:24:12 +0000
From:   Charles Keepax <ckeepax@...nsource.cirrus.com>
To:     Chancel Liu <chancel.liu@....com>
CC:     <lgirdwood@...il.com>, <broonie@...nel.org>, <perex@...ex.cz>,
        <tiwai@...e.com>, <luca.ceresoli@...tlin.com>, <ojeda@...nel.org>,
        <cmo@...exis.com>, <u.kleine-koenig@...gutronix.de>,
        <xiaolei.wang@...driver.com>, <steve@....org>,
        <chi.minghao@....com.cn>, <patches@...nsource.cirrus.com>,
        <alsa-devel@...a-project.org>, <linux-kernel@...r.kernel.org>,
        <shengjiu.wang@....com>
Subject: Re: [PATCH v2] ASoC: wm8962: Wait for updated value of
 WM8962_CLOCKING1 register

On Wed, Nov 09, 2022 at 08:13:54PM +0800, Chancel Liu wrote:
> DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate
> correct frequency of LRCLK and BCLK. Sometimes the read-only value
> can't be updated timely after enabling SYSCLK. This results in wrong
> calculation values. Delay is introduced here to wait for newest value
> from register. The time of the delay should be at least 500~1000us
> according to test.
> 
> Signed-off-by: Chancel Liu <chancel.liu@....com>
> ---

Acked-by: Charles Keepax <ckeepax@...nsource.cirrus.com>

Thanks,
Charles