lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAFBinCAQb1BXUp_Tou-UoS5AHFFE76cwv6mynoDUZp0ySwPeeQ@mail.gmail.com>
Date:   Sat, 12 Nov 2022 23:57:35 +0100
From:   Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To:     Vyacheslav Bocharov <adeep@...ina.in>
Cc:     linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/4] arm64: amlogic: mmc: meson-gx: Add core, tx, rx
 eMMC/SD/SDIO phase clock settings from devicetree data

Hi Vyacheslav,

On Thu, Nov 10, 2022 at 4:01 PM Vyacheslav Bocharov <adeep@...ina.in> wrote:
>
> The mmc driver has the same phase values for all meson platforms. However,
> some platforms (and even some boards) require different values.
Could you please elaborate which phases are per platform and which are
per board?
In this series you're only managing the core phase differently for all
AXG boards. IMO this can be achieved by extending struct
meson_mmc_data with the desired core clock phase


Best regards,
Martin

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ