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Message-ID: <CAJF2gTTOKPAqazF5w03NBzxMW7MGpoCn7vvdj=RabGrzp5WVZQ@mail.gmail.com> Date: Sat, 26 Nov 2022 08:24:57 +0800 From: Guo Ren <guoren@...nel.org> To: Samuel Holland <samuel@...lland.org> Cc: Chen-Yu Tsai <wens@...e.org>, Jernej Skrabec <jernej.skrabec@...il.com>, linux-sunxi@...ts.linux.dev, Palmer Dabbelt <palmer@...belt.com>, Conor Dooley <conor@...nel.org>, linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Rob Herring <robh+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>, Jisheng Zhang <jszhang@...nel.org>, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, Andre Przywara <andre.przywara@....com>, Albert Ou <aou@...s.berkeley.edu>, Anup Patel <apatel@...tanamicro.com>, Atish Patra <atishp@...osinc.com>, Christian Hewitt <christianshewitt@...il.com>, Conor Dooley <conor.dooley@...rochip.com>, Heinrich Schuchardt <heinrich.schuchardt@...onical.com>, Linus Walleij <linus.walleij@...aro.org>, Paul Walmsley <paul.walmsley@...ive.com>, Stanislav Jakubek <stano.jakubek@...il.com> Subject: Re: [PATCH v2 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers On Sat, Nov 26, 2022 at 7:47 AM Samuel Holland <samuel@...lland.org> wrote: > > Now that several D1-based boards are supported, enable the platform in > our defconfig. Build in the drivers which are necessary to boot, such as > the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash), > and watchdog (which may be left enabled by the bootloader). Other common > onboard peripherals are enabled as modules. > > Signed-off-by: Samuel Holland <samuel@...lland.org> > --- > > (no changes since v1) > > arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index 05fd5fcf24f9..8dfe0550c0e6 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > CONFIG_PROFILING=y > +CONFIG_ARCH_SUNXI=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_STARFIVE=y > @@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y > CONFIG_MACB=y > CONFIG_E1000E=y > CONFIG_R8169=y > +CONFIG_STMMAC_ETH=m > CONFIG_MICROSEMI_PHY=y > CONFIG_INPUT_MOUSEDEV=y > +CONFIG_KEYBOARD_SUN4I_LRADC=m > CONFIG_SERIAL_8250=y > CONFIG_SERIAL_8250_CONSOLE=y > +CONFIG_SERIAL_8250_DW=y > CONFIG_SERIAL_OF_PLATFORM=y > CONFIG_VIRTIO_CONSOLE=y > CONFIG_HW_RANDOM=y > CONFIG_HW_RANDOM_VIRTIO=y > +CONFIG_I2C_MV64XXX=m > CONFIG_SPI=y > CONFIG_SPI_SIFIVE=y > +CONFIG_SPI_SUN6I=y > # CONFIG_PTP_1588_CLOCK is not set > -CONFIG_GPIOLIB=y > CONFIG_GPIO_SIFIVE=y > +CONFIG_WATCHDOG=y > +CONFIG_SUNXI_WATCHDOG=y > +CONFIG_REGULATOR=y > +CONFIG_REGULATOR_FIXED_VOLTAGE=y > CONFIG_DRM=m > CONFIG_DRM_RADEON=m > CONFIG_DRM_NOUVEAU=m > +CONFIG_DRM_SUN4I=m > CONFIG_DRM_VIRTIO_GPU=m > CONFIG_FB=y > CONFIG_FRAMEBUFFER_CONSOLE=y > @@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y > CONFIG_USB_OHCI_HCD_PLATFORM=y > CONFIG_USB_STORAGE=y > CONFIG_USB_UAS=y > +CONFIG_USB_MUSB_HDRC=m > +CONFIG_USB_MUSB_SUNXI=m > +CONFIG_NOP_USB_XCEIV=m > CONFIG_MMC=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_PLTFM=y > CONFIG_MMC_SDHCI_CADENCE=y > CONFIG_MMC_SPI=y > +CONFIG_MMC_SUNXI=y > CONFIG_RTC_CLASS=y > +CONFIG_RTC_DRV_SUN6I=y > +CONFIG_DMADEVICES=y > +CONFIG_DMA_SUN6I=m > CONFIG_VIRTIO_PCI=y > CONFIG_VIRTIO_BALLOON=y > CONFIG_VIRTIO_INPUT=y > CONFIG_VIRTIO_MMIO=y > +CONFIG_SUN8I_DE2_CCU=m > +CONFIG_SUN50I_IOMMU=y Do we need IOMMU? Others: Reviewed-by: Guo Ren <guoren@...nel.org> > CONFIG_RPMSG_CHAR=y > CONFIG_RPMSG_CTRL=y > CONFIG_RPMSG_VIRTIO=y > +CONFIG_PHY_SUN4I_USB=m > +CONFIG_NVMEM_SUNXI_SID=y > CONFIG_EXT4_FS=y > CONFIG_EXT4_FS_POSIX_ACL=y > CONFIG_EXT4_FS_SECURITY=y > -- > 2.37.4 > -- Best Regards Guo Ren
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