linux-kernel - Re: [PATCH v1 2/3] RISC-V: resort all extensions in consistent orders

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Date:   Thu, 1 Dec 2022 12:38:24 +0100
From:   Andrew Jones <ajones@...tanamicro.com>
To:     Heiko Stübner <heiko@...ech.de>
Cc:     Conor Dooley <conor@...nel.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        linux-riscv@...ts.infradead.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        aou@...s.berkeley.edu, corbet@....net, guoren@...nel.org,
        paul.walmsley@...ive.com, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org
Subject: Re: [PATCH v1 2/3] RISC-V: resort all extensions in consistent orders

On Thu, Dec 01, 2022 at 11:47:04AM +0100, Heiko Stübner wrote:
> Am Donnerstag, 1. Dezember 2022, 10:00:41 CET schrieb Andrew Jones:
> > On Wed, Nov 30, 2022 at 11:41:25PM +0000, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley@...rochip.com>
> > > 
> > > Ordering between each and every list of extensions is wildly
> > > inconsistent. Per discussion on the lists pick the following policy:
> > > 
> > > - The array defining order in /proc/cpuinfo follows a narrow
> > >   interpretation of the ISA specifications, described in a comment
> > >   immediately presiding it.
> > > 
> > > - All other lists of extensions are sorted alphabetically.
> > > 
> > > This will hopefully allow for easier review & future additions, and
> > > reduce conflicts between patchsets as the number of extensions grows.
> > > 
> > > Link: https://lore.kernel.org/all/20221129144742.2935581-2-conor.dooley@microchip.com/
> > > Suggested-by: Andrew Jones <ajones@...tanamicro.com>
> > > Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> > > ---
> > > I could not decide between adding an alphabetical comment to each
> > > alphabetical site or not. I did it anyway. Scream if you hate it!
> > > 
> > > I also moved a static branch thingy in this version, but that should not
> > > matter, right? riightt?
> > 
> > riiighttt. And it goes away with [1] anyway.
> > 
> > [1] https://lore.kernel.org/all/20221006070818.3616-1-jszhang@kernel.org/
> 
> I'm not sure what became of that series since mid october, though noting
> that tightly coupling the patching to extensions alone might cause issues [2]
> which some of the "features" like fast-unaligned access, that are not directly
> bound to a isa-extension but to an implementation detail
> 
> [2] https://lore.kernel.org/all/1991071.yIU609i1g2@phil/

Jisheng said he'd send a refresh soon. Hopefully your comments will be
taken into consideration. It seems like we need both the concepts of
cpufeatures and extensions. Where many times a cpufeature directly maps
to an extension, but not always. Or, we could shoehorn the non-extension
cpufeatures into the extension framework by calling them "derived
extensions" or something.

> 
> 
> > 
> > > ---
> > >  arch/riscv/include/asm/hwcap.h | 12 +++++++-----
> > >  arch/riscv/kernel/cpu.c        |  4 ++--
> > >  arch/riscv/kernel/cpufeature.c |  6 ++++--
> > >  3 files changed, 13 insertions(+), 9 deletions(-)
> > > 
> > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > > index b22525290073..ce522aad641a 100644
> > > --- a/arch/riscv/include/asm/hwcap.h
> > > +++ b/arch/riscv/include/asm/hwcap.h
> > > @@ -51,14 +51,15 @@ extern unsigned long elf_hwcap;
> > >   * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
> > >   * extensions while all the multi-letter extensions should define the next
> > >   * available logical extension id.
> > > + * Entries are sorted alphabetically.
> > >   */
> > >  enum riscv_isa_ext_id {
> > >  	RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
> > > +	RISCV_ISA_EXT_SSTC,
> > > +	RISCV_ISA_EXT_SVINVAL,
> > >  	RISCV_ISA_EXT_SVPBMT,
> > >  	RISCV_ISA_EXT_ZICBOM,
> > >  	RISCV_ISA_EXT_ZIHINTPAUSE,
> > > -	RISCV_ISA_EXT_SSTC,
> > > -	RISCV_ISA_EXT_SVINVAL,
> > >  	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> > >  };
> > 
> > Unrelated to this patch, but every time I look at this enum I want to post
> > the diff below, but I haven't bothered, because this enum also goes away
> > with [1].
> > 
> > @@ -59,8 +59,9 @@ enum riscv_isa_ext_id {
> >         RISCV_ISA_EXT_ZIHINTPAUSE,
> >         RISCV_ISA_EXT_SSTC,
> >         RISCV_ISA_EXT_SVINVAL,
> > -       RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
> > +       RISCV_ISA_EXT_ID_MAX
> >  };
> > +static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX);
> 
> that sounds like a very reasonable idea ... what's keeping you? :-)

Posted :-)

Thanks,
drew