linux-kernel - Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

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Message-ID: <CAEUhbmVBLLppJdnw5CUiD+Vpj1jaGQ7FTZGVr4xT0_LaA7qSjQ@mail.gmail.com>
Date:   Tue, 6 Dec 2022 22:23:04 +0800
From:   Bin Meng <bmeng.cn@...il.com>
To:     Jiri Slaby <jirislaby@...nel.org>
Cc:     Bin Meng <bmeng@...ylab.org>, linux-kernel@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org,
        Albert Ou <aou@...s.berkeley.edu>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>
Subject: Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V

On Tue, Dec 6, 2022 at 2:47 PM Jiri Slaby <jirislaby@...nel.org> wrote:
>
> On 05. 12. 22, 6:00, Bin Meng wrote:
> ...
> > --- a/drivers/tty/serial/earlycon-arm-semihost.c
> > +++ b/drivers/tty/serial/earlycon-arm-semihost.c
> ...
> > @@ -23,7 +27,18 @@
> >    */
> >   static void smh_putc(struct uart_port *port, unsigned char c)
> >   {
> > -#ifdef CONFIG_ARM64
> > +#if defined(CONFIG_RISCV)
> > +     asm volatile("addi    a1, %0, 0\n"
> > +                  "addi    a0, zero, 3\n"
> > +                  ".balign 16\n"
> > +                  ".option push\n"
> > +                  ".option norvc\n"
> > +                  "slli    zero, zero, 0x1f\n"
> > +                  "ebreak\n"
> > +                  "srai    zero, zero, 0x7\n"
> > +                  ".option pop\n"
> > +                  : : "r" (&c) : "a0", "a1", "memory");
> > +#elif defined(CONFIG_ARM64)
> >       asm volatile("mov  x1, %0\n"
> >                    "mov  x0, #3\n"
> >                    "hlt  0xf000\n"
>
> Hmm, can we implement all those smh_putc() variants in respective
> arch/*/include/semihost.h instead?
>

I think so. Will do in v2.

Regards,
Bin