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Message-ID: <Y6B3kaPG3G3s4BKX@smile.fi.intel.com>
Date: Mon, 19 Dec 2022 16:39:13 +0200
From: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
To: Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc: linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH v1 1/1] pinctrl: intel: Use same order of bit fields for
PADCFG2
On Mon, Dec 19, 2022 at 04:34:35PM +0200, Mika Westerberg wrote:
> On Mon, Dec 19, 2022 at 02:32:29PM +0200, Andy Shevchenko wrote:
> > PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same
> > for PADCFG2 bit fields.
>
> Perhaps:
>
> No functional changes.
Sure.
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
>
> Acked-by: Mika Westerberg <mika.westerberg@...ux.intel.com>
Thank you!
--
With Best Regards,
Andy Shevchenko
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