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Message-ID: <dc2665257dc29b28822706bbbd06b81524ec2e86.camel@mediatek.com>
Date: Fri, 3 Feb 2023 03:27:29 +0000
From: Jian Yang (杨戬) <Jian.Yang@...iatek.com>
To: "helgaas@...nel.org" <helgaas@...nel.org>
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Subject: Re: [PATCH 1/2] PCI: mediatek-gen3: Add power and reset control
feature for downstream component
Dear Bjorn,
Sorry for the late response and thanks for your comment.
On Wed, 2023-01-11 at 16:14 -0600, Bjorn Helgaas wrote:
> Hi,
>
> On Wed, Jan 11, 2023 at 11:25:41AM +0800, Jian Yang wrote:
> > From: "jian.yang" <jian.yang@...iatek.com>
> >
> > Make MediaTek's controller driver capable of controlling power
> > supplies and reset pin of a downstream component in power-on and
> > power-off flow.
> >
> > Some downstream components (e.g., a WIFI chip) may need an extra
> > reset other than of PERST# and their power supplies, depending on
> > the requirements of platform, may need to controlled by their
> > parent's driver. To meet the requirements described above, I add
> > this
> > feature to MediaTek's PCIe controller driver as a optional feature.
>
> Is this delay (dsc-reset-msleep) specific to a device downstream from
> the MediaTek controller, not to the MediaTek controller itself? If
> so, it sounds like it should be a generic value that could be used by
> other drivers, too.
>
> How do you determine the value? If there's some PCIe spec that
> determines this, please include a citation to it.
Yes. This delay was defined for a downstream device (e.g., a PCIe EP)
which need an extra reset pin, not for Mediatek's PCIe controller
itself. I suppose we need to add a property in devicetree to let user
determine the delay time due to differences in requirements between
various devices.
Best regards,
Jian Yang
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