linux-kernel - Re: [PATCH 2/2] dt-bindings: PCI: mediatek-gen3: Add support for controlling power and reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAL_Jsq+eAQ-M9a+9g7Kk3GC9WjE_4mZXXrsdm4PucOJ4p2QYVQ@mail.gmail.com>
Date:   Fri, 3 Feb 2023 10:07:26 -0600
From:   Rob Herring <robh@...nel.org>
To:     Jian Yang <jian.yang@...iatek.com>
Cc:     Lorenzo Pieralisi <lpieralisi@...nel.org>,
        Jianjun Wang <jianjun.wang@...iatek.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Ryder Lee <ryder.lee@...iatek.com>,
        Krzysztof Wilczyński <kw@...ux.com>,
        linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com,
        chuanjia.liu@...iatek.com, jieyy.yang@...iatek.com,
        qizhong.cheng@...iatek.com, rex-bc.chen@...iatek.com,
        david-yh.chiu@...iatek.com
Subject: Re: [PATCH 2/2] dt-bindings: PCI: mediatek-gen3: Add support for
 controlling power and reset

On Tue, Jan 10, 2023 at 9:28 PM Jian Yang <jian.yang@...iatek.com> wrote:
>
> From: "jian.yang" <jian.yang@...iatek.com>
>
> Add new properties to support control power supplies and reset pin of
> a downstream component.
>
> Signed-off-by: jian.yang <jian.yang@...iatek.com>
> ---
>  .../bindings/pci/mediatek-pcie-gen3.yaml      | 23 +++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index 7e8c7a2a5f9b..46149cc63989 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -84,6 +84,29 @@ properties:
>      items:
>        enum: [ phy, mac ]
>
> +  pcie1v8-supply:
> +    description:
> +      The regulator phandle that provides 1.8V power to downstream component.
> +
> +  pcie3v3-supply:
> +    description:
> +      The regulator phandle that provides 3.3V power to downstream component.
> +
> +  pcie12v-supply:
> +    description:
> +      The regulator phandle that provides 12V power to downstream component.

While in some bindings we've allowed these in the host bridge node,
that is a mistake. These should be in the root port node. You probably
don't have one in DT, so add one.

> +
> +  dsc-reset-gpios:
> +    description:
> +      The reset GPIO of a downstream component.
> +    maxItems: 1
> +
> +  dsc-reset-msleep:

Doesn't the PCI spec define this time? We're talking about PERST#, right?

> +    description:
> +      The delay time between assertion and de-assertion of a downstream
> +      component's reset GPIO.
> +    maxItems: 1
> +
>    clocks:
>      minItems: 4
>      maxItems: 6
> --
> 2.18.0
>