linux-kernel - RE: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration

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Date:   Mon, 27 Mar 2023 05:34:08 +0000
From:   Swapnil Kashinath Jakhade <sjakhade@...ence.com>
To:     Roger Quadros <rogerq@...nel.org>,
        "vkoul@...nel.org" <vkoul@...nel.org>,
        "kishon@...nel.org" <kishon@...nel.org>,
        "linux-phy@...ts.infradead.org" <linux-phy@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     Milind Parab <mparab@...ence.com>
Subject: RE: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
 configuration

Hi Vinod,

> -----Original Message-----
> From: Roger Quadros <rogerq@...nel.org>
> Sent: Monday, February 20, 2023 9:50 PM
> To: Swapnil Kashinath Jakhade <sjakhade@...ence.com>;
> vkoul@...nel.org; kishon@...nel.org; linux-phy@...ts.infradead.org; linux-
> kernel@...r.kernel.org
> Cc: Milind Parab <mparab@...ence.com>
> Subject: Re: [PATCH] phy: cadence: Sierra: Add PCIe + SGMII PHY multilink
> configuration
> 
> EXTERNAL MAIL
> 
> 
> 
> 
> On 20/02/2023 16:12, Swapnil Jakhade wrote:
> > Add register sequences for PCIe + SGMII PHY multilink configuration.
> > This has been validated on TI J7 platforms.
> >
> > Signed-off-by: Swapnil Jakhade <sjakhade@...ence.com>
> 
> Reviewed-by: Roger Quadros <rogerq@...nel.org>

Could you please consider reviewing and merging this patch.

Thanks & regards,
Swapnil