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Message-ID: <20230406194938.GB405948@hirez.programming.kicks-ass.net>
Date: Thu, 6 Apr 2023 21:49:38 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Cc: Yicong Yang <yangyicong@...wei.com>,
Mark Rutland <mark.rutland@....com>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
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yangyicong@...ilicon.com, linuxarm@...wei.com,
Dan Williams <dan.j.williams@...el.com>,
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Jiucheng Xu <jiucheng.xu@...ogic.com>,
Khuong Dinh <khuong@...amperecomputing.com>,
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Anup Patel <anup@...infault.org>,
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Suzuki K Poulose <suzuki.poulose@....com>,
Liang Kan <kan.liang@...ux.intel.com>
Subject: Re: [PATCH 01/32] perf: Allow a PMU to have a parent
On Thu, Apr 06, 2023 at 05:44:45PM +0100, Jonathan Cameron wrote:
> On Thu, 6 Apr 2023 14:40:40 +0200
> Peter Zijlstra <peterz@...radead.org> wrote:
>
> > On Thu, Apr 06, 2023 at 11:16:07AM +0100, Jonathan Cameron wrote:
> >
> > > In the long run I agree it would be good. Short term there are more instances of
> > > struct pmu that don't have parents than those that do (even after this series).
> > > We need to figure out what to do about those before adding checks on it being
> > > set.
> >
> > Right, I don't think you've touched *any* of the x86 PMUs for example,
> > and getting everybody that boots an x86 kernel a warning isn't going to
> > go over well :-)
> >
>
> It was tempting :) "Warning: Parentless PMU: try a different architecture."
Haha!
> I'd love some inputs on what the x86 PMU devices parents should be?
> CPU counters in general tend to just spin out of deep in the architecture code.
For the 'simple' ones I suppose we can use the CPU device.
> My overall favorite is an l2 cache related PMU that is spun up in
> arch/arm/kernel/irq.c init_IRQ()
Yeah, we're going to have a ton of them as well. Some of them are PCI
devices and have a clear parent, others, not so much :/
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