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Message-ID: <b80ceed1-0c5a-0875-dab0-309e2318d88e@collabora.com>
Date: Thu, 25 May 2023 10:49:26 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Alexandre Mergnat <amergnat@...libre.com>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org,
linux-mediatek@...ts.infradead.org,
Kevin Hilman <khilman@...libre.com>
Subject: Re: [PATCH v8 07/10] arm64: dts: mediatek: add ethernet support for
mt8365-evk
Il 25/05/23 10:33, Alexandre Mergnat ha scritto:
> - Enable "vibr" and "vsim2" regulators to power the ethernet chip.
>
> Tested-by: Kevin Hilman <khilman@...libre.com>
> Signed-off-by: Alexandre Mergnat <amergnat@...libre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 48 +++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index 1a5769c397c2..86524cbf4354 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -88,6 +88,29 @@ optee_reserved: optee@...00000 {
> };
> };
>
> +ðernet {
> + pinctrl-0 = <ðernet_pins>;
> + pinctrl-names = "default";
> + phy-handle = <ð_phy>;
> + phy-mode = "rmii";
> + /*
> + * Ethernet and HDMI (DSI0) are sharing pins.
> + * Only one can be enabled at a time and require the physical switch
> + * SW2101 to be set on LAN position
> + * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet
> + */
> + status = "disabled";
Ouh, that's sad :-(
...but you're left with no other choice, so I agree with providing at least
the full node in case anyone wants to actually enable it by flipping the
switch on the board, so you get my
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cheers!
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + eth_phy: ethernet-phy@0 {
> + reg = <0>;
> + };
> + };
> +};
> +
> &i2c0 {
> clock-frequency = <100000>;
> pinctrl-0 = <&i2c0_pins>;
> @@ -138,6 +161,31 @@ &mt6357_pmic {
> };
>
> &pio {
> + ethernet_pins: ethernet-pins {
> + phy_reset_pins {
> + pinmux = <MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133>;
> + };
> +
> + rmii_pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0>,
> + <MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1>,
> + <MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2>,
> + <MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3>,
> + <MT8365_PIN_4_GPIO4__FUNC_EXT_TXC>,
> + <MT8365_PIN_5_GPIO5__FUNC_EXT_RXER>,
> + <MT8365_PIN_6_GPIO6__FUNC_EXT_RXC>,
> + <MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV>,
> + <MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0>,
> + <MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1>,
> + <MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2>,
> + <MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3>,
> + <MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN>,
> + <MT8365_PIN_13_GPIO13__FUNC_EXT_COL>,
> + <MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO>,
> + <MT8365_PIN_15_GPIO15__FUNC_EXT_MDC>;
> + };
> + };
> +
> gpio_keys: gpio-keys-pins {
> pins {
> pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
>
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